Wafer Level Packaging Research Articles

A Wideband Co-Linearly Polarized Full-Duplex Antenna-in-Package With High Isolation for Integrated Sensing and Communication

In this letter, a novel co-linearly polarized full-duplex antenna-in-package (AiP) with high Tx/Rx isolation and wide decoupled bandwidth is proposed for integrated sensing and communication (ISAC). Fan-out wafer-level packaging technology is employed, and the preparation process is discussed in details. To improve Tx/Rx isolation, the current direction of the patch elements is orthogonal to that of the feeding ports. Two identical 1×2 patch antenna arrays are used as Tx and Rx antennas, respectively. To further suppress mutual coupling, a decoupling loop is proposed to enhance Tx/Rx isolation. In addition, a wideband full-duplex AiP with high isolation and wide decoupled bandwidth is also proposed by using the parasitic technique and the proposed decoupling method. Prototypes are fabricated and measured to verify the proposed AiPs. The measurement results demonstrate that the proposed AiP possesses the merits of high Tx/Rx isolation (up to 53 dB), wide isolation bandwidth (up to 9.2%) and low cost, providing a foundation for chip-level applications in ISAC.

(Invited) Improvements in Thermal Budget and Film Properties Using Low Pressure Cure Technology for Advanced 3D Integration Packaging

3D advanced integration with Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP) offers multiple benefits: heterogenous chip design and stacking, increased interconnect density, and improved performance. However, it also brings new requirements for more compact form factors, low thermal budget materials and processing, and lower cost. The materials, process, and fabrication of heterogenous integration on redistribution layers (RDLs) consisting of metal and polymer dielectrics have become important enablers of the move to advanced packaging applications. To achieve the low-stress and low-cost benefits required by advanced integrated devices, thermal budgets must be reduced throughout the heterogenous integration flow -- including the dielectric curing step, which demands the use of low temperature processing and reduced cure times.In this presentation, the low temperature and low pressure thermal polymerization of dielectric polyimides used for redistribution layers (RDLs) is reviewed. Specifically, this presentation illustrates the significant impact of the low pressure cure process in reducing temperature (20° to 50° lower) and cure times (up to a 50% reduction) while providing better mechanical (elongation%, tensile strength, Young’s modulus), thermal (TG, Td 1%, Td 5%), and electrical (Dk, Df, dielectric breakdown strength - DBS) properties for different types of dielectric polyimides, including the Fujifilm LTC-9300 series, the Asahi BL-300 series, and the Toray LT-8300 and PW-1500 series. The post-curing polymerization ratio (FT-IR) and film stress were studied and are described. Finally, a proposed mechanism for the described dielectric polyimides’ polymerization under reduced pressure is discussed.Ongoing developments in design, materials, process and fabrication for FOWLP and FOPLP devices continue to drive progress in 3D heterogenous integration. This study of thermal processing of dielectric polyimides at low pressure and shorter time demonstrates a promising technique to improve overall process flow by reducing thermal budget, stress, and cost.

Crack mechanism correlated with Sn grain orientations on Ni metal surface subjected to 1000 thermal shocks

With the rapid development of 3D packaging, it is of great practical significance to understand the failure mechanism of solder joints in heterogeneous integration devices. In this study, the grain orientation and microstructure evolution of SAC305 solder joints were investigated in thermal shock tests for fan-out wafer level packaging. The heterogenous evolution of microstructure in Sn–3Ag-0.5Cu (SAC305) solder joints was investigated using electron backscattered diffraction (EBSD) and nanoindentation analysis. When the thermal shock reaches 1000 cycles, the local deformation caused the heterolattices in the joint to rotate toward the corners due to the thermal expansion. During deformation, sub-grain formation is accompanied by an increase in dislocations, the accumulation of plastic slip, and the activation of slip systems. The energy stored by this deformation is released in the form of cracks. The work in this paper provides new insights into the early stages of grain orientation, microstructural deformations and the accumulation of stored energy associated with these deformations, providing a scientific basis for the application and failure analysis of large size fan-out welded joints in complex working conditions.

Origami-Inspired Fabrication of High-Performance Wafer-Level Packaged Three-Dimensional Radio-Frequency Inductors

Planar radio-frequency (RF) on-chip inductors suffer from large electromagnetic losses, stemming from the low resistivity silicon substrate. Though it is well-known that 3-dimensional (3D) MEMS-based RF inductors offer significant performance enhancement by reducing the substrate proximity effects, they are prone to mechanical failures and often come without any appropriate packaging, leading to reliability issues. Herein, we report an approach to fabricate highly robust packaged 3D RF inductors, while relying on the concept of stress-induced self-assembly. By leveraging the large residual stresses in evaporated chromium thin films at low thicknesses (below 50 nm), we assemble the planar copper coils coated with chromium nano-layers into out-of-plane folded RF inductors, directly improving their <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor. Through measurements, we show more than three-fold ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 300%) improvement in the inductor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor after the bending. Considering the inherent fragility of suspended inductors, we then add a dedicated wafer-level polymer packaging to our inductors, to improve their mechanical robustness. Specifically, we coat a thick SU-8 layer using a quasi-static volumetric dispensing process, to embed the inductors without deforming them. Upon baking, the polymer layer solidifies, making the buried inductors extremely rigid. We show that though our inductors have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factors similar to existing MEMS inductors, their low design complexity and high strength gained via polymer packaging make them stand out among the others. This packaging technique essentially paves the way for the widespread commercialization of suspended inductors, which has been hindered in the past by their poor mechanical reliability. 2023-0018

Investigation of Vapor HF Sacrificial Etching Characteristics Through Submicron Release Holes for Wafer-Level Vacuum Packaging Based on Silicon Migration Seal

Vapor hydrogen fluoride (vHF) sacrificial SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{2}$</tex-math> </inline-formula> etching is a crucial process for wafer-level packaging based on silicon migration seal (SMS) technology. In this study, by using test samples with several kinds of test patterns and structures, the characteristics of vHF etching through release holes with a diameter of 0.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m were investigated. The results showed that through-hole etch rate had some dependence on the number and distribution of release holes, distance from the release holes, and dimension of sealed cavity, which is much different from normal vHF etching. The stiction problem in such a special case was also tested by releasing cantilever structures of different length. They were more likely to bend during through-hole etching than during normal etching. This work reveals the role of the water as both a by-product and catalyst during through-hole vHF etching. The results of this study provide important design guidelines for SMS-based MEMS packaging as well as other similar vacuum packaging technology and improve the understanding of vHF etching mechanisms. 2023-0065

The characterization of low-k thin films and their fracture analysis in a WLCSP device

The IC industry implements low dielectric constant (low-k) materials in copper/low-k interconnects to reduce the RC delay and crosstalk noises. As low-k dielectrics are weaker than traditional SiO2, measuring their mechanical properties is important for numerical simulations to evaluate the structural integrity of a package with low-k materials. In this study, we fabricated freestanding samples of low-k thin film with/without pre-cracks on both sides using lithography and exfoliation for uniaxial tension and coefficient of thermal expansion tests. The tension tests revealed that the average fracture toughness and Young's modulus of the low-k film are 1.41 MPa·m1/2 and ∼2.5 GPa, respectively. Using the measured mechanical properties, we performed a fracture analysis by a 2D finite element model for the low-k material in a wafer-level chip-size package under thermal loading. The computational results showed that the critical microcrack in the low-k layer occurs near the solder balls, where the KI increases rapidly with crack length and exceeds KIC. The results are consistent with the experimental findings in literature. The present methods can help evaluate the integrity of low-k material in a package and improve reliability.

The Effect of Porosity on the Thermal Conductivity of Highly Thermally Conductive Adhesives for Advanced Semiconductor Packages.

This study suggests promising candidates as highly thermally conductive adhesives for advanced semiconductor packaging processes such as flip chip ball grid array (fcBGA), flip chip chip scale package (fcCSP), and package on package (PoP). To achieve an extremely high thermal conductivity (TC) of thermally conductive adhesives of around 10 Wm-1K-1, several technical methods have been tried. However, there are few ways to achieve such a high TC value except by using spherical aluminum nitride (AlN) and 99.99% purified aluminum oxide (Al2O3) fillers. Herein, by adapting highly sophisticated blending and dispersion techniques with spherical AlN fillers, the highest TC of 9.83 Wm-1K-1 was achieved. However, there were big differences between theoretically calculated TCs that were based on the conventional Bruggeman asymmetric model and experimentally measured TCs due to the presence of voids or pores in the composites. To narrow the gaps between these two TC values, this study also suggests a new experimental model that contains the porosity effect on the effective TC of composites in high filler loading ranges over 80 vol%, which modifies the conventional Bruggeman asymmetric model.

Development of ANN-Based Warpage Prediction Model for FCCSP via Subdomain Sampling and Taguchi Hyperparameter Optimization.

This study aims to establish an accurate prediction model using artificial neural networks (ANNs) to effectively and efficiently predict the process-induced warpage of a flip-chip chip-scale package (FCCSP). To enhance model performance, a novel subdomain-based sampling strategy and Taguchi hyperparameter optimization are proposed in the ANN algorithm. To simulate the warpage behavior the FCCSP during fabrication, a process modeling approach is proposed, where the viscoelastic behavior of the epoxy molding compound is included, in which the viscoelastic properties are determined using dynamic mechanical measurement. In addition, the temperature-dependent thermal-mechanical properties of the materials in the FCCSP are assessed through thermal-mechanical analysis and dynamic mechanical analysis. The modeled warpage results are verified by the warpage measurement. Next, warpage parametric analysis is performed to identify the key factors most affecting warpage behavior for use in the construction of the warpage prediction model. Moreover, the advantages of the proposed sampling and hyperparameter tuning approaches are proved by comparing with other existing models, and the validity of the developed ANN-based deep learning warpage prediction model is demonstrated through a validation dataset.

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study.

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

Nonlinear Dynamics of Large-Angle Circular Scanning With an Aluminum Nitride Micro-Mirror

This paper introduces a model for nonlinear dynamics of a resonant micro-mirror designed for large-angle circular scanning. The mirror is driven by aluminum nitride thin-films within a chip-scale vacuum package, which permits large scan angles to be achieved at low voltages, but with substantial nonlinearity in the mirror’s dynamic response. A nonlinear mirror model is proposed and analyzed to identify major trends in mirror performance and implications for mirror design. Analysis focuses on coupling between two axes, which has not been closely examined for multi-axis micro-mirrors. Coupling between axes is found to be capable of augmenting scan amplitude or causing mirror response to collapse from a circular scan patter to an ellipse or line scan, depending on relative strength of model parameters. Good agreement is achieved between modeled and experimental micro-mirror response, with scan amplitudes near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 13 degrees under 1.5 V excitation.2022-0181

Interfacial Delamination Validation on Fan-Out Wafer-Level Package Using Finite Element Method

Fan-out wafer-level package is a very promising packaging technology with good thermal and electrical performance. The fan-out wafer-level package exhibits beneficial features such as low profile, high I/O density, low cost, and efficient computing. The package experiences large temperature variations in the assembly phase which causes internal stresses. In particular, the mismatch between the coefficient of thermal expansion of the epoxy molding compound and the substrate due to the cool down phase of the cure process causes the internal stresses in the package. These internally induced stresses result to interfacial delamination. In this study, the interfacial delamination on a fan-out wafer-level package right after post mold cure of glass wafer was evaluated using the stress-based damage index through the finite element analysis in the ANSYS software package. The model was validated by comparing the simulation result of the glass wafer warpage to the existing experimental result from literature. From the warpage simulation of the glass wafer, the region on the package with high stress level was located and examined which may cause interfacial delamination. The maximum shear stress and principal stress at the epoxy molding compound and the Silicon chip interface was found to exceed the adhesion strength. This indicates that the interfacial delamination is inevitable. The information obtained from the stress analysis of molded wafer provides insight for the possible interfacial failure of fan-out wafer-level package in the individual package when subjected to thermomechanical loads.

Protected Wafer Level Chip Scale Packaging (P-WLCSP)

With the advent of bumped die, new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip), CBGA (ceramic ball grid array), and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), was built on the wafer with no active side protection, evolving to single sided protection from a package built on the wafer3 , which transitioned to redistribution PSB (passivation stress buffer)4 . PSBs were implemented in FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability, performance evolved to CSP5 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. An example of fully protected die CSP (without substrates or leadframes) encapsulated in mold compound is M-series utilizing a FO (fan out) processes and eWLB.6,7 To obtain higher reliability 6-sided die protection afforded by FO processes require die reconstitution, expensive tapes, molding, and other operations which can feasibly be eliminated in a WLCSP protected FI process assuming full encapsulation can be attained on the original device wafer. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected fan-in. SoP-TM produces the thinnest and lowest cost fully protected FI. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This paper includes background on the evolution of CSP, comparison of SOTA (state of the art) FI processes including SoP-TM and builds on low-cost wafer level adaptive process works and reliability data presented on the new SoP-TM process earlier this year.8,9 First article electrical reliability test data for P-WLCSP, adaptive processing of micro-bump pads, and potential applications in hybrid modules will be shown.

An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging

With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a critical processing step. As the process has matured, significant efforts have been made for optimization in terms of both production and cost. This is especially true for photoresist stripping, since thick photoresists are needed to pattern high aspect ratios and must be removed in subsequent steps to expose underlying metal films. In this study, the removal of a thick negative tone photoresist with solder pillar plated wafers were investigated using a dimethyl sulfoxide blend with a quaternary ammonium hydroxide. Emphasis was placed on exploring the feasibility of an extended bath life beyond 7 days. Coupon level beaker tests were used to provide insight into the swelling and dissolution mechanisms with fresh and aged chemistry. Additionally, several chemistries were compared to examine the effect of the quaternary ammonium hydroxide. Based on these findings, chemical aging studies were performed on 300 mm wafers using a highly customizable single wafer processing tool that combined soaking and a high-pressure spray processing to potentially prolong the bath age even further. In addition to stripping efficiency at extended bath life, the compatibly with pillar structures and seed layers is investigated. Results from the study highlight potential methods to extend bath life while maintaining photoresist stripping efficiency.

Novel Temporary Bonding Film Adapted to Xenon Flash Lamp De-bonding System for FOWLP Application

Temporary bonding film (TBF) is one of the key materials for assembly process of fan out wafer level package (FOWLP). In this paper, we have proposed a novel TBF and xenon flash lamp de-bonding system. The TBF was mainly composed of cross-linkable and low-polarity polymers to meet the various requirement for not only easy peeling-off after assembly but also stability against thermal and chemical environment exposed in FOWLP process. In order to evaluate applicability of the developed material, die-first/face up test wafer was assembled. As a result, it was found that the TBF has high stability and can be de-bonded by xenon light irradiation. In addition, the die shift through assembly process was within the estimated range. These results offer that the developed TBF is practically applicable for FOWLP assembly process.

Inspection Solution for 2μm RDL from Wafer-Level to Panel-Level Fan-out Process

In the advanced packaging industry, both fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) have grown quickly in recent years since they are compatible with largescale, low-cost manufacturing and are key enablers for ultra-thin and high-density packages. However, the commercialization of the fan-out process continues to face technical challenges with the rapid adoption of finer pitch and width of the Cu redistribution layer (RDL) in die-first or die-last integration approaches. AOI has been widely used in the advanced packaging industry as a major tool for defect inspection during various process steps. The conventional bright field and dark field imaging techniques suffer from a high nuisance rate for RDL inspection; in many cases, the RDL metal grain size could be larger than the defect of interest, and the interferences from underneath the pattern, such as bottom RDL layers or molding compounds, can increase the difficulties of defect detection. In this paper, we present Onto Innovation’s innovative fluorescence technology to enhance contrasts between organic material, such as polyimide, or photoresists and metals that enable fine-pitch RDL inspection with increased accuracy by eliminating nuisance defects. By using powerful fluorescence technology, in conjunction with higher resolution, high-definition inspection (HDI) technology, fine-pitch RDL defect inspections on both wafer-level and panel-level packaging were studied and shown to enable accelerated development cycles in the R&amp;D stage, as well enable rapid yield enhancements in the HVM environment.

Die-embedded packaging using Corning® multi-layered glass

Die-embedded (DE) packaging technologies in recent years have ventured into advanced packaging structures, such as fan-out wafer level packages (FOWLPs) or package-on-packages (PoPs). They offer higher density at lower costs, despite many challenges, such as the die-shift and warpage problems often observed during the molding process, caused by the high shrinkage and high coefficients of thermal expansion (CTEs) of the molding materials. This in turn makes it difficult to accurately mount the high-density fine-pitch bumps and adversely affects the overall yield, especially in processes using large-size substrates. Glass, known for its superior dimensional and thermal stability and its low or tunable CTEs, can be advantageous in reducing die-shift and warpages as opposed to other alternative material solutions for the molding process. In this paper, we propose a packaging solution based on a glass substrate incorporating a plurality of precisely dimensioned cavities, with a chip positioned in each cavity to prevent them from shifting during processing. Corning® Adaptive Formed Glass (AFG), a laminate glass with a unique clad/core/clad structure, allows for effectively forming cavities with high dimensional precision and positional accuracies as well as surface flatness through a wet etch process. Using a 0.5mm thick laminate Corning® AFG glass, we successfully designed and fabricated three types of DE packages with lab scale tools at Korea Electronics Technology Institute (KETI): single- and double-sided DE packages, and package-on-packages (POPs). High etching selectivity over 20:1, which was achieved by carefully designing the core and clad glass compositions, enabled a wet-etch cavity forming process with accurate cavity depths and flat bottom surfaces (&lt; ± 2.5μm) with relative ease. A double-sided DE package with a total thickness of 600μm was fabricated with two 125μm-thick IC chips, one embedded on each side of the substrate, and connected by metallized through glass vias (TGVs). A POP measured at 5.1×5.1×1.27 mm3 was also successfully demonstrated by using two built-in double-sided DE packages joined by flip-chip bonding, equivalent to stacking four layers of conventional single-sided DE packages. The double-sided DE packages and POPs presented in this paper are believed to be the world’s first demonstration on glass. The work also manifests the immense potential of Corning® AFG glass in enabling higher density IC packaging and large-size panel-level (or wafer-level) packaging.

A high-uniformity, high-purity copper pillar ECP process with limited acid concentration

The requirements for wafer-level packaging (WLP) are becoming more and more stringent both from a sustainability perspective and process performance. For instance, there is a demand for continuous process improvement for within die uniformity (WID) and operating in a low acid environment for copper pillar plating. Antagonistic these requests are; however, we must devise novel ECP techniques and additive designs to meet such ambitious targets. The additives consist of an accelerator, suppressor, and leveler. The systematic use of Linear Sweep Voltammetry (LSV) aided the study of the electrochemical response to screen the additives and determine the Wagner number (Wa) in the current density region of interest. In addition, the rigorous use of the Design of Experiment (DOE) enabled us to determine the concentrations for combining this new leveler and suppressor with the accelerator. Owing to designing the right leveler and suppressor, we controlled the free acid concentration at 10% (100 g/L) while maintaining the WID below 2.5% and controlling the within-feature (WIF) less than 1µm (~2.0%), using a deposition rate of approximately 2.0 µm/min, to various wafer patterns with various aspect ratios and layouts. Lastly, the resulting film properties are as crucial as ECP performance. SIMS studies support a deficient level of inclusion in the copper film with a total impurity of 3.1 ppm, including C, O, N, S, and Cl. Therefore, when studied with a solder cap, the Kirkendall void performance was outstanding based on minimal voids post 10X reflow cycles and high-temperature storage. The shear stress test measuring the bonding between the copper and its pad on the wafer is 18.4 gf/mil2.

The Study of Highest Thickness Photo Resist for Cu Post of Fan-Out Wafer Level Packaging

The mobile device’s limited thermal budget hardly allows the use of a high-performance application (AP) at its full speed. However, as artificial intelligence technologies has been rapidly applied for mobile devices, the demand like high-speed and large-capacity signal processing is continuously increasing. Therefore, controlling the heat generation of AP chip is becoming a key factor, and it is necessary to develop a Re-Distribution Layer (RDL) based Fan-Out Package (FOPKG) structure that does not increase the thickness of the package while maximizing the die thickness for heat dissipation. The height of Cu post is getting higher for the production of FOPKG that can apply thick die, and in this study, the world’s thickest photoresist material (&gt;350um thickness) was developed for the production of Cu post (&gt;300um thickness). The effect of light transmittance of the photoresist and the effect of solubility depending on the molecular structure of the main polymer were studied for lithography process of thick photoresist. Based on the understanding of this thick photoresist behavior, the optimal liquid type photoresist composition was developed. Through lithography evaluation based on thick photoresist characteristics, deep-hole via implementation and Cu electro-plating were performed to obtain a yield of Cpk 1.27 in the AP product design applied wafer. Depending on this in-depth understanding and experimentation on thick photoresist, it is possible to build an advanced research foundation of increasing the photoresist thickness and finer Cu post pitch to secure heat dissipation characteristics and improve the degree of freedom of architecture.

A novel hybrid method to integrate delicate MEMS components into a FOWLP

A steep increase in IoT- and smart devices fuels the need for ever more miniaturized and highly integrated microelectronic packages. Fan-Out technology is well suited for this task, as it allows for heterogeneous (co-)integration of sensor elements and corresponding circuitry. Following a Chip-First approach in Fan-Out Wafer-Level Packaging (FOWLP), protection of delicate sensor areas during compression molding and formation of redistribution layers (RDL) becomes a key part of the manufacturing process chain. Such areas include thin membranes, antireflective coatings, air bridges or media access for gas sensors. We demonstrate a novel packaging method for a MEMS pressure sensor with corresponding ASIC (application-specific integrated circuit). We integrate vertical interconnect elements (VIE), instead of employing laser drilling for via formation and thereby avoid debris and reduce the overall package thickness. The hybrid approach, at heart, relies on a structured adhesive layer, onto which components are placed prior to compression molding. Due to its thermal and mechanical stability, the patterned thin film adhesive serves as a (first) dielectric layer. Process development includes warpage management to allow for laser debonding from temporary glass carriers and RDL processing compatible with delicate MEMS surfaces. Summarizing, we present a novel process variant to avoid common issues related to sensor surface integrity using Fan Out technology and thus allow for highly miniaturized System in Package (SiP) concepts with sensor integration by mold embedding.

A high-efficiency transformer-in-package isolated DC-DC converter using glass-based fan-out wafer-level packaging

A transformer-in-package (TiP) isolated direct current–direct current (DC-DC) converter using glass-based fan-out wafer-level packaging (FOWLP) is proposed. By using 3-layer redistribution layers (RDLs), both the transformer and interconnections are built without an additional transformer chip, and the converter only has 2 dies: a transmitter (TX) chip and a receiver (RX) chip. The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density. Moreover, the transformer built by the RDLs achieves a high quality factor (Q) and high coupling factor (k), and the efficiency of the converter is thus improved. The TX and RX chips were implemented in a 0.18 µm Biopolar CMOS DMOS (BCD) process and embedded in a compact package with a size of 5 mm × 5 mm. With an output capacitance of 10 µF, the converter achieves a peak efficiency of 46.5% at 0.3 W output power and a maximum delivery power of 1.25 W, achieving a maximum power density of 50 mW/mm2.