Wireless Network-on-Chip Architecture Research Articles

Tree-based wireless NoC architecture: enhancing scalability and latency

Tree-based wireless NoC architecture: enhancing scalability and latency

Evaluation of Performance of different routing Algorithm using Noxim

One of the primary methods for examining and testing novel ideas in the Network-on-Chip space is simulation. Noxim simulator enables the analysis of performance for both established wired NoC and new WiNoC architectures. User can modify the size of the network, size of the packet, routing algorithm, various strategy selection and packet injection rate. The simulator evaluates NoCs in terms of various parameters of Network throughput, delay etc. In particular, the user can obtain various assessment metrics such as overall number of received packets/flits, global average throughput, max/min global delay, consumption of total energy. and so on. In comparison to traditional mesh NoC, this paper examines how different routing methods and WiNoC sizes affect network traffic distributions. We analyze PIR, Network throughput parameters of 8*8 mesh networks for various routing algorithms and its impacts are investigated. Simulation of Mesh wireless NOC architecture is validated.

A low-power WNoC transceiver with a novel energy consumption management scheme for dependable IoT systems

Wireless network-on-chip architectures (WNoCs), by combining wired and wireless modules and links, provide fast and efficient communication infrastructures for complex on-chip systems such as various IoT and intelligent systems. The most challenging step of designing high-performance and energy-efficient WNoCs is the structure of transceivers. In fact, transceivers and wired routers are the most power-hungry elements in WNoCs; therefore, any cut-down of power consumption in transceivers and routers significantly reduce the power consumption of WNoCs. In this paper, a low-power transceiver for WNoC is designed and then, a high-performance and configurable energy consumption management scheme for the transceiver is proposed. In the designed transceiver, various strategies are employed at both circuit-level and also at architectural-level for reducing static and dynamic power consumption. The proposed energy management scheme controls the activity and tunes the voltage level of the power supply of each module, in a distributed and dynamic manner. The evaluation results demonstrate that a WNoC utilizing the proposed scheme provides lower energy consumption, less latency, and higher reliability and higher network throughput compared to both of relevant single-chip and multi-chip WNoC architectures, at the cost of negligible impact on silicon area.

Design of a Novel Wireless NoC Architecture for Chip Multiprocessor

The Network on chip is a new communication method of System on Chip. It is the main part of multi-core technology. A large number of embedded cores can be combined on a single chip. Due to the multi-hop characteristics of communication, there are some problems in the design of traditional NoC, such as high latency and power consumption. Thus, to handle the communication problem of long-distance transmission of traditional NoC, wireless Networks on Chip (WiNoC) has been proposed. Using WiNoC to design the multi-core System on Chip can significantly reduce the latency and energy consumption of the network. The advantage of using wireless network on chip is to replace the multi-hop path of traditional network on chip with wireless single hop link. However, due to the limited space on the chip and the cost, it is very important to determine the optimal number and correct location of wireless hubs. In this paper, we propose a new method to obtain the optimum configuration of a WiNoC by using the Co-evolutionary Algorithms (CA) and a wireless NoC architecture based on mesh. This work examines the effect of VC and sub-net size on WiNoC performance efficiency and energy under different packet injection rate (PIR) and the number of cores (64, 144 and 256). The simulation experiment of the algorithm proposed in the whole architecture has been implemented on the Noxim platform.

Design of a Novel Wireless Noc Architecture for Chip Multiprocessor

Design of a Novel Wireless Noc Architecture for Chip Multiprocessor

Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip

The communication performance over conventional long-distant routers cannot satisfy the requirements of future multi-core systems. Wireless Network-on-Chip (WiNoC) architecture with CMOS compatible transceivers is utilized to obtain significant improvement in on-chip data transfer for multi-core systems. The wireless routers (WRs) in WiNoC architecture provide wireless shortcuts to alleviate the latency of multi-hop communications. Despite the additional bandwidth of wireless shortcuts, the WRs are prone to congestion due to the limited number of wireless channels and the shared use of these channels under unbalanced load. On the other hand, network performance will be severely degraded when the presence of head-of-line (HOL) blocking. In this paper, we establish a congestion pre-avoidance and load-balanced wireless network-on-chip architecture. To implement such architecture in our network, firstly, we propose an dynamic XY-YX routing algorithm detour WR to pre-avoid the additional traffic flow of the wireless router; Secondly, the virtual output queue scheme is adopted to handle HOL blocking, and on this basis we design a wireless router micro-architecture; Finally, a threshold-based load-balanced mechanism is designed, which uses the number of buffered flit as a guideline to avoid unbalance load. Through system-level simulations, the results demonstrate that the proposed WiNoC architecture can mitigate negative effect of congestion in WR. And with appropriate hardware overhead, network transmission latency and network throughput are significantly improved.

Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip

Wireless Network-on-Chip (WiNoC) are being examined for parallel applications to improve the performances by reducing multi-hop latency. Wireless nodes handle massive data transmission assignment, the data bandwidth and energy efficiency of the WiNoC architecture can be improved by establishing wireless links to respond to dynamically changing traffic patterns. Among them, the wireless token mechanism is widely used, since it would take little additional hardware overhead and simple operation process. However, the traditional wireless token mechanism is a time-division-multiplexed fair strategy, and cannot well cope with non-uniform traffic patterns. In this paper, a priority-based dynamic media access control (MAC) mechanism in wireless network-on-chip is architected by redefining MAC mechanism, which aims to make wireless MAC protocols more suitable for non-uniform traffic patterns. Experimental results show that the proposed scheme in this paper guarantees the network performance equivalent to the traditional token mechanism in random traffic mode, and the network throughput is increased by 14%–15% in the hotspot mode. Compared with the traditional token mechanism, the average packet delay is greatly reduced before the saturation point with little extra hardware overhead introduced simultaneously.

Flow control and scheduling mechanism to improve network performance in wireless NoC

Today's, a promising solution, namely wireless network-on-chip (WiNoC) is utilized in multi-core systems to overcome the constraints of conventional on-chip networks. In WiNoC architectures, wireless routers (WRs) provide high capacity wireless links to reduce the latency of multi-hop communications. However, the buffer size of the WR antenna is limited, and under heavy traffic loads, it's filled and congestion occurs. On the other hand, network performance is degraded severely in the presence of head-of-line (HOL) blocking. Therefore, flow control and scheduling mechanisms are vital for improving the performance of WiNoCs. In this study, a flow control scheme based on an active queue management algorithm, and a priority-based scheduling strategy are suggested. The proposed mechanisms are evaluated under uniform and Bit-complement traffic patterns with different packet injection rate. The simulation results show that the proposed schemes have a significant impact on performance parameters, such as latency and throughput. Moreover, the saturation packet injection rate in WiNoC with four WRs is improved to about 33% under uniform traffic and is increased up to about 50% under the Bit-complement traffic pattern. This is increased by 16 and 50% in WiNoC with 16 WRs for uniform and Bit-complement traffic patterns, respectively, compared to the conventional WiNoCs.

A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips

Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC architectures differ in the position of the wireless routers and how they interact with other routers. So, the placement of wireless interfaces is an important step in designing WiNoC architectures. In this paper, we propose a simulated annealing (SA) placement method which considers the routing algorithm as a factor in designing cost function. To evaluate the proposed method, the Noxim, which is a cycle-accurate network-on-chip simulator, is used. The simulation results show that the proposed method can reduce flit latency by up to 24.6% with about a 0.2% increase in power consumption.

Cm3WiNoCs: Congestion-Aware Millimeter-Wave Multichannel Wireless Networks-on-Chip

Millimeter-wave (mm-Wave) technology has been widely adopted in recent wireless network-on-chip (WiNoC) design since it is fully compatible with current CMOS process. By employing efficient channel multiplexing mechanisms, the performance of WiNoCs can be improved. However, such improvement is very limited since the wireless channels are generally shared by multiple pairs of communicating nodes and as the network size scales up, the multiplexing mechanisms perform worse. In this work, more physically achievable mm-Wave channels are introduced in WiNoCs, based on which, a high-performance millimeter-wave multichannel WiNoC architecture is elaborated which includes designs of topology, routing and MAC mechanism. Besides, to relieve the congestion in hubs, a congestion-aware adaptive channel selection (CAACS) mechanism is also proposed. Simulation results show that such an architecture increases the saturated throughput by 16%~98% and by introducing the CAACS mechanism, the saturated throughput can be further improved by up to 17%. The average packet delay is also significantly reduced while just negligible area and energy overhead are produced.

H2WNoC: A honeycomb hardware-efficient wireless network-on-chip architecture

Network-on-chips (NoCs) have emerged as communication backbones for enabling massive parallelism and high degree of integration in many-core chips. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on NoCs performance by long delay and high power consumption especially in large systems. To alleviate these problems, different solutions such as wireless network-on-chip (WiNoC) designs have been proposed. WiNoCs benefit from long-range, high bandwidth and low power wireless links to solve problems corresponding to wired communications. Most of the WiNoC architectures have been designed based on mesh topology, while, honeycomb topology provides more energy-efficient NoC architecture with higher throughput than mesh topology, but, as we will show, a honeycomb-based WiNoC, by itself, does not reduce the amount of utilized hardware resources and delay. In this paper, we propose a hardware-efficient WiNoC with honeycomb topology, namely, H2WNoC aiming at reducing hardware resources, network cost, delay, and also energy consumption. Considering different performance parameters, cycle-accurate-based evaluations are performed for the proposed architecture; H2WNoC is compared with the traditional mesh WiNoC, as the baseline, and also with three state-of-the-art WiNoC architectures. Furthermore, design space exploration of the proposed architecture is performed. Performance evaluations indicate that H2WNoC utilizes less hardware resources, consumes less amount of energy and improves both throughput and delay, compared to the other WiNoC architectures. Moreover, the obtained results show that the proposed architecture outperforms wired NoCs either with mesh or honeycomb topology.

Design and performance evaluation of Mesh-of-Tree-based hierarchical wireless network-on-chip for multicore systems

Hybrid Wireless Network on Chip (WNoC) architecture has been proposed as a promising solution for addressing on-chip communication problems in many multicore systems. The choice of infrastructure topology directly affects the performance gain of the architecture. For exploiting the benefits offered by both mesh and tree topologies, we employ Mesh-of-Tree (MoT) topology as a new communication infrastructure for hybrid WNoC architectures. Moreover, long-distance links are effectively added to the MoT topology to form wireless MoT architecture and an appropriate communication routing scheme is presented to employ this paradigm. The performance and the system cost of the proposed WNoC architecture have been evaluated and compared with other notable WNoC architectures through comprehensive network-level simulations. Experimental results demonstrate the effectiveness of this wireless MoT architecture under both synthetic and realistic traffic patterns in terms of network throughput, latency, and power consumption. The results demonstrate that the proposed architecture can approximately achieve 35% improvement in saturation throughput, 58% reduction in transmission latency, and 43% improvement in power consumption over a wireline MoT-NoC, on average.

A novel hierarchical architecture for Wireless Network-on-Chip

In the architecture of Networks-on-Chip (NoCs), wired structure and multi-hop communications can lead to high power consumption and latency. Wireless NoC (WiNoC) architecture is a new alternative to solve these challenges. In this architecture, long-range wireless links are used instead of multi-hop wired paths. In this paper, a combination of several topologies are investigated to develop an efficient hierarchical structure for the architecture of WiNoC. The performances of considered hierarchical structures are compared under different traffic patterns. Finally, by using the Analytic Hierarchy Process (AHP) technique, a new hierarchical wireless NoC is proposed. In the proposed architecture, hierarchical structure and wireless links with high bandwidth are regarded as two significant factors for reducing the number of hops between distant nodes. Based on the results of simulations, the proposed hierarchical structure has better efficiency than other WiNoC architectures.

A novel Wireless Network-on-Chip architecture with distributed directories for faster execution and minimal energy

Wireless Network-on-Chip (WNoC) architectures are introduced to improve performance by reducing the core-to-core communication latency. Conventional WNoCs broadcast messages that increase bandwidth-traffic, communication delay, and power consumption. Studies show that directory-based architectures have potential to address message broadcasting and improve performance. This work proposes a novel WNoC architecture with distributed directories (WNoC-DDs) that supports wireless communications to enhance faster execution by reducing latency. VisualSim software package is used to model and simulate the proposed WNoC-DDs, a WNoC with centralized directory (WNoC-CD), and a traditional 2D mesh by processing different communication scenarios. The proposed architecture helps reduce the total hop count and unwanted broadcasting among nodes in a WNoC-DDs. Experimental results show that the proposed WNoC-DDs reduces communication delay up to 20.54% and 5.40%, respectively, when compared to mesh and WNoC-CD. Similarly, the proposed WNoC-DDs reduces power consumption up to 73.56% and 19.97%, respectively, when compared to mesh and WNoC-CD.

A hierarchical architecture based on traveling salesman problem for hybrid wireless network-on-chip

The increased latency and power consumption are the major challenges of traditional wired Network-on-Chip (NoC). The Wireless NoC (WNoC) architecture is regarded as a novel approach to solve NoC problems. In this paper, hybrid hierarchical structures are studied. The considered topologies for the first level of the hierarchy include: Chordal Ring of degree 3 (CR) and Ring-Connected Cycles (RCC). On the second level of the hierarchy, inspired by the Traveling Salesman Problem (TSP), a new method is proposed to form the topology. Considering the NP-Hard nature of the problem, the hybrid PS-ACO algorithm is used to obtain the desired tour. In this paper, the uniform random traffic is used as the synthetic traffic pattern and the 3-tuple traffic is used as a real application traffic pattern. The simulation results show that the proposed structure has fewer wired links and considerably increased efficiency compared with a wired mesh topology in NoC.

Improving Energy Efficiency in Wireless Network-on-Chip Architectures

Wireless Network-on-Chip (WiNoC) represents a promising emerging communication technology for addressing the scalability limitations of future manycore architectures. In a WiNoC, high-latency and power-hungry long-range multi-hop communications can be realized by performance- and energy-efficient single-hop wireless communications. However, the energy contribution of such wireless communication accounts for a significant fraction of the overall communication energy budget. This article presents a novel energy managing technique for WiNoC architectures aimed at improving the energy efficiency of the main elements of the wireless infrastructure, namely, radio-hubs. The rationale behind the proposed technique is based on selectively turning off, for the appropriate number of cycles, all the radio-hubs that are not involved in the current wireless communication. The proposed energy managing technique is assessed on several network configurations under different traffic scenarios both synthetic and extracted from the execution of real applications. The obtained results show that the application of the proposed technique allows up to 25% total communication energy saving without any impact on performance and with a negligible impact on the silicon area of the radio-hub.

Interference-Aware Wireless Network-on-Chip Architecture Using Directional Antennas

Wireless Network-on-Chip (WiNoC) has been recently introduced for addressing the scalability limitations of conventional multi-hop NoC architectures. Existing WiNoC architectures generally use millimeter-wave antennas without significant directional gains, along with token passing protocol to access the shared wireless medium. This limits the achievable performance benefits since only one wireless pair can communicate at a time. It is also not practical in the immediate future to arbitrarily scale up the number of non-overlapping channels by designing transceivers operating in disjoint frequency bands in the millimeter-wave spectrum commonly adopted for on-chip wireless interconnects. Consequently, we explore the use of directional antennas whereby multiple wireless interconnect pairs can communicate simultaneously. However, concurrent wireless communications can result in interference. This can be minimized in NoC by optimal placement of wireless interfaces (WIs) to maximize performance while minimizing interference. To address this, we propose an interference-aware WIs placement algorithm with routing strategy for WiNoC architecture by incorporating directional planar log-periodic antennas (PLPAs). This directional wireless network-on-chip (DWiNoC) architecture enables point-to-point links between transceivers and hence multiple wireless links can operate at the same time without interference.

Multicast-Aware High-Performance Wireless Network-on-Chip Architectures

Today's multiprocessor platforms employ the network-on-chip (NoC) architecture as the preferable communication backbone. Conventional NoCs are designed predominantly for unicast data exchanges. In such NoCs, the multicast traffic is generally handled by converting each multicast message to multiple unicast transmissions. Hence, applications dominated by multicast traffic experience high queuing latencies and significant performance penalties when running on systems designed with unicast-based NoC architectures. Various multicast mechanisms such as XY-tree multicast and path multicast have already been proposed to enhance the performance of the traditional wireline mesh NoC incorporating multicast traffic. However, even with such added features, the multihop nature of the wireline mesh NoC leads to high network latencies and thus limits the achievable system performance. In this paper, to sustain the high-bandwidth and high-throughput requirements of emerging applications, we propose the design of a wireless NoC (WiNoC) architecture incorporating necessary multicast support. By integrating congestion-aware multicast routing with network coding, the WiNoC is able to efficiently handle heavy multicast injections. For applications running with a broadcast-heavy Hammer cache coherence protocol, the proposed multicast-aware WiNoC achieves an average of 47% reduction in message latency compared with the XY-tree-based multicast-aware mesh NoC. This network level improvement translates into a 26% saving in full-system energy delay product.

A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures

Wireless Network-on-Chip (WNoC) architectures have emerged as a promising interconnection infrastructure to address the performance limitations of traditional wire-based multihop NOCs. Nevertheless, the WNoC systems encounter high failure rates due to problems pertaining to integration and manufacturing of wireless interconnection in nano-domain technology. As a result, the permanent failures may lead to the formation of any shape of faulty regions in the interconnection network, which can break down the whole system. This issue is not investigated in previous studies on WNoC architectures. Our solution advocates the adoption of communication structures with both node and link on disjoint paths. On the other hand, the imposed costs of WNoC design must be reasonable. Hence, a novel approach to design an optimized fault-tolerant hybrid hierarchical WNoC architecture for enhancing performance as well as minimizing system costs is proposed. The experimental results indicate that the robustness of this newly proposed design is significantly enhanced in comparison with its the fault-tolerant wire-based counterparts in the presence of various faulty regions under both synthetic and application-specific traffic patterns.

Exploiting antenna directivity in wireless NoC architectures

Wireless Network-on-Chip (WiNoC) is an emerging on-chip communication paradigm and a candidate solution for dealing with the scalability problems which affect current and next generation many-core architectures. In a WiNoC, the transceivers that allow the conversion between electrical and radio signals, account for a significant fraction of the total communication energy budget. In particular, the transmitting power for wireless communications is strongly affected by the orientation of the antennas. This paper studies the impact of antennas orientation on energy figures of a WiNoC architecture and performs a design space exploration for determining the optimal orientation of the antennas in such a way to minimize the communication energy consumption. Experiments have been carried out on state-of-the-art WiNoC topologies, on both synthetic and real traffic scenarios, and validated by means of a commercial field solver simulator. When the antennas are optimally oriented, up to 80% energy saving (as compared to the case in which antennas have all the same orientation) has been observed.