Abstract

Millimeter-wave (mm-Wave) technology has been widely adopted in recent wireless network-on-chip (WiNoC) design since it is fully compatible with current CMOS process. By employing efficient channel multiplexing mechanisms, the performance of WiNoCs can be improved. However, such improvement is very limited since the wireless channels are generally shared by multiple pairs of communicating nodes and as the network size scales up, the multiplexing mechanisms perform worse. In this work, more physically achievable mm-Wave channels are introduced in WiNoCs, based on which, a high-performance millimeter-wave multichannel WiNoC architecture is elaborated which includes designs of topology, routing and MAC mechanism. Besides, to relieve the congestion in hubs, a congestion-aware adaptive channel selection (CAACS) mechanism is also proposed. Simulation results show that such an architecture increases the saturated throughput by 16%~98% and by introducing the CAACS mechanism, the saturated throughput can be further improved by up to 17%. The average packet delay is also significantly reduced while just negligible area and energy overhead are produced.

Highlights

  • As silicon technology scales down into deep sub-micron nodes, the number of cores integrated on a single chip has increased phenomenally and traditional bus-based interconnects1 cannot satisfy the performance demands due to low bandwidth, high delay and bad scalability

  • We present a high-performance wireless networkon-chip (WiNoC) architecture composed of topology, routing and MAC mechanism designs based on the mm-Wave multichannel transceiver proposed in [9]

  • (3) when the performance of mm-Wave single-channel WiNoCs can only be improved limitedly by channel multiplexing, we present a comprehensive and in-depth discussion about mm-Wave multichannel WiNoC architecture aiming at providing new ideas for high-performance mm-Wave WiNoC design

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Summary

INTRODUCTION

As silicon technology scales down into deep sub-micron nodes, the number of cores integrated on a single chip has increased phenomenally and traditional bus-based interconnects cannot satisfy the performance demands due to low bandwidth, high delay and bad scalability. All these three channels can be adopted to establish a congestion-aware millimeter-wave triple-band wireless networks-on-chip. When the tail flit of a packet in the antenna transmitting buffer (ABTx) completes its transmission, signal ls_tail_flit goes high and the wireless interface (WI) can be used for the transmission of a token flit generated by the TMU Such a MAC mechanism greatly improves the utilization of mm-Wave channels which leads to significant enhancement of the network performance. It can be concluded that if the wireless interface supports a higher data rate, smaller ABTx/ABRx buffers can just satisfy the performance demands of the network

CONGESTION-AWARE ADAPTIVE CHANNEL SELECTION
DEADLOCK ANALYSIS
Findings
CONCLUSION

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