Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip

Abstract

The communication performance over conventional long-distant routers cannot satisfy the requirements of future multi-core systems. Wireless Network-on-Chip (WiNoC) architecture with CMOS compatible transceivers is utilized to obtain significant improvement in on-chip data transfer for multi-core systems. The wireless routers (WRs) in WiNoC architecture provide wireless shortcuts to alleviate the latency of multi-hop communications. Despite the additional bandwidth of wireless shortcuts, the WRs are prone to congestion due to the limited number of wireless channels and the shared use of these channels under unbalanced load. On the other hand, network performance will be severely degraded when the presence of head-of-line (HOL) blocking. In this paper, we establish a congestion pre-avoidance and load-balanced wireless network-on-chip architecture. To implement such architecture in our network, firstly, we propose an dynamic XY-YX routing algorithm detour WR to pre-avoid the additional traffic flow of the wireless router; Secondly, the virtual output queue scheme is adopted to handle HOL blocking, and on this basis we design a wireless router micro-architecture; Finally, a threshold-based load-balanced mechanism is designed, which uses the number of buffered flit as a guideline to avoid unbalance load. Through system-level simulations, the results demonstrate that the proposed WiNoC architecture can mitigate negative effect of congestion in WR. And with appropriate hardware overhead, network transmission latency and network throughput are significantly improved.