Design of a Novel Wireless NoC Architecture for Chip Multiprocessor

Abstract

The Network on chip is a new communication method of System on Chip. It is the main part of multi-core technology. A large number of embedded cores can be combined on a single chip. Due to the multi-hop characteristics of communication, there are some problems in the design of traditional NoC, such as high latency and power consumption. Thus, to handle the communication problem of long-distance transmission of traditional NoC, wireless Networks on Chip (WiNoC) has been proposed. Using WiNoC to design the multi-core System on Chip can significantly reduce the latency and energy consumption of the network. The advantage of using wireless network on chip is to replace the multi-hop path of traditional network on chip with wireless single hop link. However, due to the limited space on the chip and the cost, it is very important to determine the optimal number and correct location of wireless hubs. In this paper, we propose a new method to obtain the optimum configuration of a WiNoC by using the Co-evolutionary Algorithms (CA) and a wireless NoC architecture based on mesh. This work examines the effect of VC and sub-net size on WiNoC performance efficiency and energy under different packet injection rate (PIR) and the number of cores (64, 144 and 256). The simulation experiment of the algorithm proposed in the whole architecture has been implemented on the Noxim platform.