Wire Bond Research Articles

The Influence and Application of Bond Wires Failure on Electrothermal Characteristics of IGBT Module

The bond wires failure is one of the most common failure modes of the insulated gate bipolar transistor (IGBT) module, which will cause an increase in the overall ON-state voltage drop V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> , and it is generally believed to not affect the junction-to-case thermal resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">thjc</sub> . The measured V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> mainly consists of two parts: the voltage drop of the IGBT chip V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_Chip</sub> and that of the bond wire V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_wire</sub> ; the influence of bond wires failure on V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> should be discussed and explained in two parts. However, these actual measurement parameters are not considered before. In this article, the impact mechanism of bond wires failure on electrothermal characteristics of the IGBT module is analyzed with the help of realistic simulation models and experiment verification. The results show that the bond wires failure only affects V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_wire</sub> , and the impact on V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_Chip</sub> is small, which can be ignored. Meanwhile, the increase in the virtual junction temperature is not caused by the increase in the power loss of the IGBT chip but by the increase in the current density of bond feet, which is caused by the decrease in the effective contact area. Besides, the measured R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">thjc</sub> is not the intrinsic thermal resistance but slightly smaller than the intrinsic thermal resistance, and it decreases as the bond wires failure. Furthermore, the proposed mechanism can provide method guidance for the separation strategy of concurrent failure modes of IGBT modules only by monitoring the ON-state voltage drop.

Practical Challenges of High-Power IGBT’s I-V Curve Measurement and Its Importance in Reliability Analysis

This paper examines the practical challenges of simplified setups aimed at achieving high-power IGBTs’ IC–VCE curve. The slope of this I–V curve (which is defined as on-resistance RCE) and the point where the VCE–VGE curve visibly bends (threshold gate voltage) can be suitable failure precursor parameters to determine an IGBT’s health condition. A simplified/affordable design for these specific measurements can be used for in-situ condition monitoring or field testing of switching devices. First, the possible I–V curve measurement methods are discussed in detail in order to prevent self-heating. The selected design includes two IGBTs in which the high-side IGBT was the device under test (DUT) with a constant gate voltage (VGE) of 15 V. Then, the low-side IGBT was switched by a short pulse (50 μs) to impose a high-current pulse on the DUT. The VCE–VGE curve was also extracted as an important failure-precursor indicator. In the next stage, a power-cycling test was performed, and the impact of degradation on the IGBT was analyzed by these measurement methods. The results show that after 18,000 thermal cycles, a visible shift in I–V curve can be seen. The internal resistance increased by 13%, while the initial collector-emitter voltage and voltage at the knee point in the VCE–VGE curve slightly changed. It is likely that in our case, during the performed power-cycling test and aging process, the bond wires were most affected, but this hypothesis needs further investigation.

Polymer-Based Biocompatible Packaging for Implantable Devices: Packaging Method, Materials, and Reliability Simulation.

Polymer materials attract more and more interests for a biocompatible package of novel implantable medical devices. Medical implants need to be packaged in a biocompatible way to minimize FBR (Foreign Body Reaction) of the implant. One of the most advanced implantable devices is neural prosthesis device, which consists of polymeric neural electrode and silicon neural signal processing integrated circuit (IC). The overall neural interface system should be packaged in a biocompatible way to be implanted in a patient. The biocompatible packaging is being mainly achieved in two approaches; (1) polymer encapsulation of conventional package based on die attach, wire bond, solder bump, etc. (2) chip-level integrated interconnect, which integrates Si chip with metal thin film deposition through sacrificial release technique. The polymer encapsulation must cover different materials, creating a multitude of interface, which is of much importance in long-term reliability of the implanted biocompatible package. Another failure mode is bio-fluid penetration through the polymer encapsulation layer. To prevent bio-fluid leakage, a diffusion barrier is frequently added to the polymer packaging layer. Such a diffusion barrier is also used in polymer-based neural electrodes. This review paper presents the summary of biocompatible packaging techniques, packaging materials focusing on encapsulation polymer materials and diffusion barrier, and a FEM-based modeling and simulation to study the biocompatible package reliability.

Bond wire lift-off monitoring based on intersection point movement characteristic in IGBT module

Condition monitoring (CM) the insulated-gate bipolar transistor (IGBT) module is of vital significance to improve the reliability of power electronics system. Collector–emitter on-state voltage VCE,ON is a frequently employed failure precursor to identify the bond wire aging. In this paper, a method of separating VCE,ON is proposed to monitor the bond wire lift-off of IGBT module. Firstly, based on the circuit structure of IGBT module, the VCE,ON is divided into voltage drop across IGBT chip VChip and voltage drop across bond wire VBW. Secondly, the working principle of IGBT chip is investigated, and the calculation method of voltage drop across P-i-N diode VPiN is proposed. Finally, the VChip is analyzed, and information provided by collector current IC at the IC–VChip curve intersection point that is not affected by solder layer fatigue is adopted to monitor the lift-off degree of bond wire. The feasibility of the above methods is verified by theory and experiment.

Hybrid external-cavity lasers (ECL) using photonic wire bonds as coupling elements

Combining semiconductor optical amplifiers (SOA) on direct-bandgap III–V substrates with low-loss silicon or silicon-nitride photonic integrated circuits (PIC) has been key to chip-scale external-cavity lasers (ECL) that offer wideband tunability along with small optical linewidths. However, fabrication of such devices still relies on technologically demanding monolithic integration of heterogeneous material systems or requires costly high-precision package-level assembly, often based on active alignment, to achieve low-loss coupling between the SOA and the external feedback circuits. In this paper, we demonstrate a novel class of hybrid ECL that overcome these limitations by exploiting 3D-printed photonic wire bonds as intra-cavity coupling elements. Photonic wire bonds can be written in-situ in a fully automated process with shapes adapted to the mode-field sizes and the positions of the chips at both ends, thereby providing low-loss coupling even in presence of limited placement accuracy. In a proof-of-concept experiment, we use an InP-based reflective SOA (RSOA) along with a silicon photonic external feedback circuit and demonstrate a single-mode tuning range from 1515 to 1565 nm along with side mode suppression ratios above 40 dB and intrinsic linewidths down to 105 kHz. Our approach combines the scalability advantages of monolithic integration with the performance and flexibility of hybrid multi-chip assemblies and may thus open a path towards integrated ECL on a wide variety of integration platforms.

Impact of Thermo-Mechanical Stress Due to Probing and Wire Bonding on CUP Devices

Recently, the circuit under pad (CUP) designs are getting very popular because they could save lots of silicon especially for high-density and high-complexity applications. Polysilicon is a material widely used in many electronic device components. When such devices are placed underneath the bond pads, it is highly expected not to show any change in the electrical behavior due to any kind of thermo-mechanical stresses such as probing or wire bonding mainly during the process of packaging. This article presents a detailed investigation of such impacts on a polysilicon resistor placed underneath the bond pads. The standard meander-shaped polysilicon resistor was used as a test vehicle. In this article, different stress-causing factors such as probing insertions, probing temperature, and wire bond materials were investigated in detail. The impact of such thermo-mechanical stresses is simulated using Comsol to understand the stress phenomenon and for qualitative analysis. Then, the wafer-level silicon testing was carried out to quantify the impact of such thermo-mechanical stresses using a standard design of experiments (DOEs). The impact in terms of change in resistance of the polysilicon resistor of two different widths (5 and 0.42 μm) for two different bond pad metal options viz. Middle thickness metal (METMID) (thickness of 880 nm) and thick metal (METTHK) (thickness of 3000 nm) was investigated. The percent change in resistance was observed to be very negligible after multiple probing attempts and probe temperatures. However, after wire bonding, up to ~14% change in resistance was observed when copper was used as the wire bonding material. Nevertheless, this percent change was still well within the reliability specification limit set by Joint Electron Device Engineering Council (JEDEC), which is widely used in the industry. This detailed investigation will help CUP designers choose the correct back end of line (BEOL) metal options and also wire bonding material upfront and accordingly plan their design margins.

Thermal Influence Coefficients-Based Electrothermal Modeling Approach for Power Electronics

An inverter or converter achieves the desired dc-ac or dc-dc conversion as required by electric and hybrid electric vehicles. This conversion is typically performed using semiconductor switches such as Insulated Gate Bipolar Transistors (IGBTs) modules consisting of transistors and diodes. Multiple transistors-diode pairs are integrated under a common copper base plate (also referred to as case). As power density increases, the heat dissipation of each device is influenced by other devices. The heat loss from semiconductor devices needs to be effectively dissipated to the ambient to maintain the temperature of IGBTs and diodes within acceptable limits (mentioned by the component manufacturer or based on the desired thermal margin in design). The over-temperature of the IGBT junction causes reliability issues resulting in solder fatigue and bond wire wear-out. The current work comprises predicting the temperature-dependent heat loss (electrothermal modeling) and thermal management techniques to dissipate these losses effectively to the ambient. An influence coefficient matrix is defined for liquid-cooled IGBT modules and used to estimate the die-to-die thermal influence. The IGBT module's heat distribution and its effect on the die temperature are studied for dc-dc and dc-three phase ac conversion.

Load-dependent power transfer efficiency for on-chip coils

This paper presents a theory for the power transfer efficiency of printed circuit board coils to integrated circuit coils, with focus on load-dependence for low-power single-chip systems. The theory is verified with electromagnetic simulations modelled on a 350 nm CMOS process which in turn are verified by measurements on manufactured integrated circuits. The power transfer efficiency is evaluated by on-chip rectification of a 151 MHz signal transmitted by a spiral coil on a printed circuit board at 10 mm of separation to an on-chip coil. Such an approach avoids the influence of off-chip parasitic elements such as bond wires, which would reduce the accuracy of the evaluation. It is found that there is a lower limit for the load below which reducing the power consumption of on-chip circuits yield no increase in voltage generated at the load. For the examined process technology, this limit appears to lie around 56 kOmega. The paper is focused on the analysis and verification of the theory behind this limit. We relate the results presented in this work to the application of wireless single-chip temperature monitoring of power semiconductors and conclude that such a system would be compatible with this limit.

A SiC Double-Sided Stacked Wire-Bondless Power Module for High-Frequency Power Electronic Applications

Abstract This article reports a double-sided stacked wire-bondless power module package for silicon carbide (SiC) power devices to achieve low parasitic inductance and improved thermal performance for high-frequency applications. The design, simulation, fabrication, and characterization of the power module are presented. A half-bridge module based on the SiC power MOSFETs is demonstrated with minimized parasitic inductance. Double-sided cooling paths are used to maximize heat dissipation. Besides conventional packaging materials used in the power module fabrication, a low-temperature cofired ceramic (LTCC) and nickel-plated copper balls are used in this module package. The LTCC acts as an interposer providing both electrical and thermal routings. The nickel-plated copper balls replace bond wires as the electrical interconnections for the SiC power devices. The electrical and thermo-mechanical simulations of the power module are performed, and its switching performance is evaluated experimentally.

Design of Single Input Multiple Output Buck Converter with Light Load Efficiency

The major demand for portable electronics devices such as pagers, laptops, cellular phones etc. Single input multiple output (SIMO) converter will be proposed to give different supply voltages while keep up prolong battery life. A single-discharge (SDC) control scheme is introduce to simplify the Single inductor multiple output design, attain to low cross regulation, and to support board range of loads with decent efficiency of power. A Single discharge control single input multiple output buck converter with 4 outputs composed of comparators, phased-locked loop, finite state machine (FSM) controller, and an output stage. In addition to the basic switching functions, the FSM controller provides a state skipping feature to allow no-load regulation. Single input multiple output converter is available for less cost and used for maintaining long battery life and they are growing in vast range with rich feature portable electronic device. The design of converter is designed for limited range for prolonged battery life. The SIMO converters are used for the reduction of cost and switching losses, hence improve system efficiency. In our study, we proposed buck converter topology with single input of 24v and multiple output of 12v and 5v. The 12v voltage is used for electric vehicles. In electric vehicles it is used in horns and headlights. 5v voltage is used for small signal and stability analysis. The simulated conversion efficiency for peak power is 86% the power ranging for output is 50 to 300mW. The ICs exhibit has a low measured peak efficiency of 73% and cross regulation of 0.24 mV/mA because of parasitic bond wire resistance. The proposed system is simulated in MATLAB/Simulink software.

An Anti-Interference Online Monitoring Method for IGBT Bond Wire Aging

Due to the constant changes of the environment and load, the insulated-gate bipolar transistor (IGBT) module is subjected to a large amount of junction temperature (Tj) fluctuations, which often leads to damage to the bond wires. The monitoring parameters of IGBTs are often coupled with Tj, which increases the difficulty of monitoring IGBTs’ health status online. In this paper, based on the collector current (Ic) and collector-emitter on-state voltage (Vce_on) online monitoring circuit, an online monitoring method of IGBT bond wire aging against interference is proposed. First, the bond wire aging model is established, and the Vce_on is selected as the monitoring parameter. Secondly, taking a three-phase inverter circuit as an example, the Vce_on and Ic waveforms of the IGBT module are monitored in real time, and the process of online monitoring is introduced accordingly. Finally, the experimental results output by RT-LAB indicate that the method proposed in this paper can accurately identify the aging state of IGBT bond wires under different conditions.

Estimation of the thermal gap when soldering waveguide elements

This paper proposes a method for determining the required gap between the elements of the waveguide path during its assembly by soldering. The need for a thermal gap is defined by difference in mass and dimensional parameters of the elements to be connected, due to which a significant no uniformity of heating and thermal deformations occur. The no uniformity of thermal deformations leads to jamming of one element in another, therefore, the heating time and the size of the thermal gap are need to be determined. The diameter of the solder wire is determined according to the size of the thermal gap and the required fillet of the soldered seam. The performed numerical calculations of the stress state of the obtained soldered seam showed the absence of stress concentration. Mechanical tests have confirmed the high strength of soldered seam.

Controllable Transfer of MOx Nanowires on Microhotplate-Based Gas Sensing Devices

Introduction SnO2 nanowires (NWs) have been synthesized and implemented on CMOS-based gas sensors devices with gold inter-digital electrode structures (IDES). For the implementation process of NWs a polydimethylsiloxane-based stamping transfer was employed with help of a Condor Sigma bond tester. The multi-nanowire gas sensor has demonstrated sensitivity for toluene concentrations as low as 100 ppb. The transfer method applied in this work is one step further from previous manual transfer [1] to the industrial adaptation of the process. Materials and substrates A two-step synthesis was applied to prepare SnO2 nanowires, as described elsewhere [2]. The gas sensing substrate was a commercial chemical sensor platform provided by ams AG, Austria - a 2x2 mm micro-hotplate chip with a Pt-based microheater and Pt-IDES with an electrode width and the distance between the electrode fingers both 5 µm. SnO2 NWs were transferred on the IDES-structure with a PDMS stamp, prepared by 1:10 standard recipe and cut into 3x3mm pieces. Transfer of SnO2 NWs A Condor Sigma bond tester tool was employed to transfer SnO2 NWs. The PDMS-stamp was glued on a specific tool of the bond tester, which is usually employed for testing wire bond connections. The PDMS stamp was pressed with well controlled parameters (force, distance and position) onto the substrate with MOx NWs in order to collect the NWs with the stamp. Afterwards the NWs were transferred onto the gas sensing substrate with maximal force of 0.7N and 10s time of contact between the stamp and the micro-hotplate substrate, which resulted in NW transfer and interconnection to the electrodes. Gas measurement Gas measurements were performed by an automatized setup, with synthetic air (80% N2, 20% O2) as a background gas and a constant flow rate of 1000 sccm. Three different humidity levels of 25, 50 and 75% were investigated in the presence of 5 different toluene concentrations – 0.05, 0.1, 0.5, 1 and 5 ppm. The temperature of the microhotplate was kept constant at 300°C. Response was calculated as follows:R = (Rair - Rgas)/Rair *100%where Rair is a resistance of the sensor in synthetic air before the gas pulse and Rgas is a resistance of the sensor in the presence of a test gas at the end of a gas pulse. Two independent sensors were measured, prepared by the same technique. Results and Conclusions The Condor Sigma bond tester enabled precise manipulation of the PDMS NW transfer stamp not only in all 3 axis but also by using force sensor. Due to the high precision of the machine the transfer process could be performed with high precision and control without damage to the micro-hotplate. This demonstrates that such a NW transfer process is suited for realization of NW-based chemical sensor devices. The response towards toluene is shown in Fig.1. The multi-nanowire based devices are able to sense a gas concentration as low as 100 ppb (where the threshold limit value for Switzerland is 50 ppm [3]). There is also visible dependence towards humidity – but it is not as high as for toluene – i.e. for 5 ppm of toluene the mean response for both sensors is 9%, 8% and 8% for 25, 50 and 75% rH levels, respectively. Presently the work is focused on the NWs transfer on CMOS-based microhotplate array chips. Acknowledgements This work was partly performed within the project “FunkyNano – Optimized Functionalization of Nanosensors for Gas Detection by Screening of Hybrid Nanoparticles” funded by the FFG - Austrian Research Promotion Agency (Project No. 858637). References Sosada-Ludwikowska, R. Wimmer-Teubenbacher, M. Sagmeister, A. Köck, Transfer Printing Technology as a Straightforward Method to Fabricate Chemical Sensors Based on Tin Dioxide Nanowires, Sensors (2019), 19, 3049; doi: 10.3390/s19143049Köck, A. Tischner, T. Maier, M. Kast, C. Edtmaier, C. Gspan, G. Kothleitner, Atmospheric pressure fabrication of SnO2-nanowires for highly sensitive CO and CH4 detection, Sensors and Actuators B: Chemical (2009), 138 no. 1, pp. 160–167 (2009); doi: 10.1016/j.snb.2009.02.055Schweizerische Unfallversicherungsanstalt (SUVA): Grenzwerte – Aktuelle MAK- und BAT-Werte für Toluol. Available online: https://www.suva.ch/de-CH/material/Richtlinien-Gesetzestexte/grenzwerte-am-arbeitsplatz-aktuelle-werte (accessed on 29.11.2019) Figure 1

An Adaptive Electrothermal Model for Estimating the Junction Temperature of Power Device

The insulated-gate bipolar transistor (IGBT) module that is sensitive to high temperature has been identified as one of the most fragile parts in electric vehicles. In this article, a new adaptive electrothermal model that is independent of solder aging is proposed to acquire junction temperature in real time for the health management of IGBTs. Compared with the traditional adaptive electrothermal model, the proposed model can update the parameters of thermal resistance and thermal capacitance simultaneously to adapt to the solder aging conditions. Besides, the update process just relies on the measured case temperatures, which is cost-effective and is not affected by the degradation of bond wires and gate oxide. Simulation and experimental results are provided to verify the effectiveness of the proposed method. Under the test conditions, the estimated errors of the junction temperature by the proposed model are reduced by about 60% compared with the traditional model.

Influence of power cycling ageing on the current and voltage transitions during hard switching of IGBT devices

In this paper, the influence of ageing by PCT (Power Cycling Test) on the hard switching behavior of IGBT (Insulated Gate Bipolar Transistor) devices, especially the current change rate di/dt and voltage change rate dv/dt during the switching process, is investigated with standard DC-PCT and a PCT with superimposed switching losses. 1200 V IGBTs with two different package forms are used for the PCTs to stimulate two common failure modes: discrete devices with the bond wire failures and modules without baseplate to trigger the solder layer degradation. To evaluate the hard switching behavior of the IGBTs, a DPT (double pulse test) is repetitively performed after a specific number of cycles at the same test conditions to determine the influence of power cycling ageing. The experimental results show that the current and voltage transient transitions of IGBT devices during hard switching are independent of the power cycling ageing.

On the Direct Extrusion of Solder Wire from 52In-48Sn Alloy

In this article, technology for producing wire and rod solder from 52In-48Sn alloy has been developed and investigated in the conditions of small-scale production. The use of direct extrusion of wire and rods instead of traditional technology for producing solder, which includes pressing, rolling and drawing, can significantly reduce the fleet of required equipment. Using only a melting furnace and a hydraulic press, solder wires and rods can be produced in various sizes. Shortening the production cycle allows you to quickly fulfill small orders and be competitive in sales. This article develops a mathematical model of direct extrusion, which allows you to calculate the extrusion ratio, extrusion speed and pressing force. The results of modeling the process of extrusion of wire Ø2.00 mm and rods Ø8.0 mm made of 52In-48Sn alloy are presented. The temperature of the solder and the tool is simulated in software QForm based on the finite element method. Experimental results of manufacturing Ø2.0 mm solder wire and Ø8.0 mm rods are presented. The microstructure of the direct extruded solder is a eutectic of phases γ and β. Energy-dispersive X-ray spectroscopy (EDS) mapping of the 52In-48Sn alloy showed that the solder obtained by direct extrusion has a uniform distribution of structural phases. The developed technology can be used in the manufacture of wires and rods from other low-melting alloys.

Woven Electroanalytical Biosensor for Nucleic Acid Amplification Tests.

Fiber-based biosensors enable a new approach in analytical diagnostic devices. The majority of textile-based biosensors, however, rely on colorimetric detection. Here a woven biosensor that integrates microfluidics structures in combination with an electroanalytical readout based on a thiol-self-assembled monolayer (SAM) for Nucleic Acid Amplification Testing, NAATs is shown. Two types of fiber-based electrodes are systematically characterized: pure gold microwires (bond wire) and off-the-shelf plasma gold-coated polyester multifilament threads to evaluate their potential to form SAMs on their surface and their electrochemical performance in woven textile. A woven electrochemical DNA (E-DNA) sensor using a SAM-based stem-loop probe-modified gold microwire is fabricated. These sensors can specifically detect unpurified, isothermally amplified genomic DNA of Staphylococcus epidermidis (10 copies/µL) by recombinase polymerase amplification (RPA). This work demonstrates that textile-based biosensors have the potential for integrating and being employed as automated, sample-to-answer analytical devices for point-of-care (POC) diagnostics.

Sinterconnects: All-Copper Top-Side Interconnects Based on Copper Sinter Paste for Power Module Packaging

Copper sinter paste has been recently established as a robust die-attach material for high -power electronic packaging. This paper proposes and studies the implementation of copper sinter paste materials to create top-side interconnects, which can substitute wire bonds in power packages. Here, copper sinter paste was exploited as a fully printed interconnect and, additionally, as a copper clip-attach. The electrical and thermal performances of the copper-sinter paste interconnections (“sinterconnects”) were compared to a system with wire bonds. The results indicate comparable characteristics of the sinterconnect structures to the wire-bonded ones. Moreover, the performance of copper sinterconnects in a power module was further quantified at higher load currents via finite element analysis. It was identified that the full-area thermal and electrical contact facilitated by the planar sinterconnects can reduce ohmic losses and enhance the thermal management of the power packages.

Proof of concept for through silicon vias in application-specific integrated circuits for hard x-ray imaging detectors

Application-specific integrated circuits (ASICs) are commonly used to efficiently process the signals from sensors and detectors in space. Wire bonding is a space-qualified technique of making interconnections between ASICs and their substrate packaging board for power, control, and readout of the ASICs. Wire bonding is nearly ubiquitous in modern space programs, but their exposed wires can be prone to damage during assembly and subject to electric interference during operations. Additional space around the ASICs needed for wire bonding also impedes efficient packaging of large arrays of detectors. Here, we introduce the through silicon vias (TSV) technology that replaces wire bonds and eliminates their shortcomings. We have successfully demonstrated the feasibility of implementing TSVs to existing ASIC wafers (a.k.a. a via-last process) developed for processing the x-ray signals from the x-ray imaging CdZnTe detectors on the Nuclear Spectroscopic Telescope Array small explorer telescope mission that was launched in 2012. While TSVs are common in the semiconductor industry, this is the first (to our knowledge) successful application for astrophysics imaging instrumentation. We expect that the TSV technology will simplify the detector assembly and thus will enable significant cost and schedule savings in assembly of large area CdZnTe detectors.

Silicone encapsulation of thin-film SiO x , SiO x N y and SiC for modern electronic medical implants: a comparative long-term ageing study

Objective. Ensuring the longevity of implantable devices is critical for their clinical usefulness. This is commonly achieved by hermetically sealing the sensitive electronics in a water impermeable housing, however, this method limits miniaturisation. Alternatively, silicone encapsulation has demonstrated long-term protection of implanted thick-film electronic devices. However, much of the current conformal packaging research is focused on more rigid coatings, such as parylene, liquid crystal polymers and novel inorganic layers. Here, we consider the potential of silicone to protect implants using thin-film technology with features 33 times smaller than thick-film counterparts. Approach. Aluminium interdigitated comb structures under plasma-enhanced chemical vapour deposited passivation (SiO x , SiO x N y , SiO x N y + SiC) were encapsulated in medical grade silicones, with a total of six passivation/silicone combinations. Samples were aged in phosphate-buffered saline at 67 ∘C for up to 694 days under a continuous ±5 V biphasic waveform. Periodic electrochemical impedance spectroscopy measurements monitored for leakage currents and degradation of the metal traces. Fourier-transform infrared spectroscopy, x-ray photoelectron spectroscopy, focused-ion-beam and scanning-electron- microscopy were employed to determine any encapsulation material changes. Main results. No silicone delamination, passivation dissolution, or metal corrosion was observed during ageing. Impedances greater than 100 GΩ were maintained between the aluminium tracks for silicone encapsulation over SiO x N y and SiC passivations. For these samples the only observed failure mode was open-circuit wire bonds. In contrast, progressive hydration of the SiO x caused its resistance to decrease by an order of magnitude. Significance. These results demonstrate silicone encapsulation offers excellent protection to thin-film conducting tracks when combined with appropriate inorganic thin films. This conclusion corresponds to previous reliability studies of silicone encapsulation in aqueous environments, but with a larger sample size. Therefore, we believe silicone encapsulation to be a realistic means of providing long-term protection for the circuits of implanted electronic medical devices.