Memory Window Width Research Articles

Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle >106, retention >106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µCcm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

Graphdiyne particles as nano-floating gates for high-performance nonvolatile organic field-effect transistor memory

Graphdiyne particles (GDYP), newcomers of carbon family, were employed as nano-floating gates in organic field-effect transistor (OFET) memories. The charge-trapping layer was prepared by blending GDYP into a polystyrene (PS) matrix. The effect of GDYP doping ratio on memory performances was investigated, and the OFET memory with the optimal doping concentration of the GDYP (0.3 mg/mL) exhibits ambipolar memory behavior with a wide memory window as large as 86 V, excellent retention time over 104 s with a high ON/OFF current ratio of 7.5 × 105. This work demonstrates that graphdiyne is a promising charge-trapping material for high-performance nonvolatile OFET memory devices.

Enabling the wide memory window and long endurance in hafnia-based FeFET from the perspective of interfacial layer

In this research, we employed AlOx and AlON thin films as interfacial layers (IL) in ferroelectric capacitors to achieve a significantly large memory window (MW) of 4.5 V and endurance up to 108 cycles. By manipulating the IL materials, we obtain different intensity of voltage drop across the IL, thus changes the depolarization field in HZO, leading to increased MW. Furthermore, we integrated AlO x /AlON into ferroelectric FETs and confirmed that AlO x /AlON indeed enhances the threshold voltage difference (∆V T ), while maintaining an endurance of 109 cycles. this study shed light on design guidelines for large MW memory devices.

A carbonyl-decorated two-dimensional polymer as a charge-trapping layer for non-volatile memory storage devices with a high endurance and wide memory window.

The charge-trapping mechanism in conjugated polymers is a performance obstacle in many optoelectronic devices harnessed for non-volatile memory applications. Herein, a carbonyl-decorated organic 2D-polymer (TpDb)-based charge-trapping memory device has been developed with a wide memory window (3.2 V) with low programming and erasing voltages of +3/-2 and -3/+2. The TpDb was synthesized by a potentially scalable solid-state aldol condensation reaction. The inherent structural defects and the semi-conjugated nature of the enone network in TpDb offer effective charge-trapping through the localization of charges in specific functional groups (CO). The interlayer hydrogen bonding enhances the packing density of the 2D-polymer layers thereby improving the memory storage properties of the material. Furthermore, the TpDb exhibits excellent features for non-volatile memory applications including over 10 000 cycles of write/read endurance and a prolonged retention performance of 104 seconds at high temperatures (100 °C).

A study on memory characteristics of hybrid-based charge trap-type organic non-volatile memory device according to gate stack thickness

Continuous research on charge trap-type organic non-volatile memory (CT-ONVM) devices aims to achieve highly reliable large memory window characteristics, comparable to inorganic-based poly-silicon/oxide/nitride/oxide/silicon (SONOS) devices. This study introduces hybrid-based ultra-thin films via the initiated chemical vapor deposition (iCVD) process as the gate-stack of highly reliable CT-ONVM devices. One method of achieving a wide memory window is by increasing the gate-stack thickness of hybrid-based gate stacks of CT-ONVM devices. However, thick gate-stacks (>50 nm) do not dramatically change the memory window and deteriorate the subthreshold swing (S.S.) compared to thin gate-stacks (<30 nm). Electrons passing through the thickened tunneling dielectric layer (TDL) generate a large number of interface traps, which degrade the S.S. and hinder the charge injection into the charge trapping layer (CTL). This contributes to the non-change of the memory window to increase along with the leakage through the blocking dielectric (BDL) to the gate electrode. Based on electrical characterization, our group proposes directions and follow-up plans to effectively improve the memory window and reliability of CT-ONVM devices.

A sustainable biomass-based electret for face mask and non-volatile transistor memory

An electret filter on the middle layer of disposable medical face masks has a similar function to the charge storage layer on the transistor memory devices. Both applications require a polymer electret to trap charges so that it could establish electrostatic attraction to effectively enhance the filtration efficiency of face mask or modulate the electrical behaviours of transistor memory. By virtue of that very same function, we demonstrate the charge storage performance and memory characteristics of transistor memory using the electret filters of face mask material, from the non-renewable polypropylene (PP) to the biomass-based polymers. We demonstrate dextrin, a biomass-derivative, as a sustainable alternative electret. Due to dextrin being produced natural starch products, it is a renewable material that is biocompatible and eco-friendly. Furthermore, by adding sodium methylsiliconate (SMS), the hydrophobic blended dextrin-SMS transistor memory can maintain inherent prolonged electrostatic charges for over 100 days along with relatively wide memory window of 39.5 V. Ultimately, the non-woven nanofiber electret filter using dextrin-SMS can be successfully produced using an industrial compatible electrospinning technique combined with the addition of polyethylene oxide (PEO) to improve the electrospinability of the mat filter and potentially utilized for future biodegradable face masks and green electronics.

Nano-scale charge trapping memory based on two-dimensional conjugated microporous polymer

There is a growing interest in new semiconductor nanostructures for future high-density high-performance flexible electronic devices. Two-dimensional conjugated microporous polymers (2D-CMPs) are promising candidates because of their inherent optoelectronic properties. Here, we are reporting a novel donor–acceptor type 2D-CMP based on Pyrene and Isoindigo (PI) for a potential nano-scale charge-trapping memory application. We exfoliated the PI polymer into ~ 2.5 nm thick nanoparticles (NPs) and fabricated a Metal–Insulator–Semiconductor (MIS) device with PI–NPs embedded in the insulator. Conductive AFM (cAFM) is used to examine the confinement mechanism as well as the local charge injection process, where ultrathin high-κ alumina supplied the energy barrier for confining the charge carrier transport. We have achieved a reproducible on-and-off state and a wide memory window (ΔV) of 1.5 V at a relatively small reading current. The device displays a low operation voltage (V < 1 V), with good retention (104 s), and endurance (103 cycles). Furthermore, a theoretical analysis is developed to affirm the measured charge carriers’ transport and entrapment mechanisms through and within the fabricated MIS structures. The PI–NPs act as a nanoscale floating gate in the MIS-based memory with deep trapping sites for the charged carriers. Moreover, our results demonstrate that the synthesized 2D-CMP can be promising for future low-power high-density memory applications.

Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3 for stacked in-memory computing array

In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfer. Nevertheless, it necessitates a high-density memory array to effectively manage large data volumes. Here, we present a stacked ferroelectric memory array comprised of laterally gated ferroelectric field-effect transistors (LG-FeFETs). The interlocking effect of the α-In2Se3 is utilized to regulate the channel conductance. Our study examined the distinctive characteristics of the LG-FeFET, such as a notably wide memory window, effective ferroelectric switching, long retention time (over 3 × 104 seconds), and high endurance (over 105 cycles). This device is also well-suited for implementing vertically stacked structures because decreasing its height can help mitigate the challenges associated with the integration process. We devised a 3D stacked structure using the LG-FeFET and verified its feasibility by performing multiply-accumulate (MAC) operations in a two-tier stacked memory configuration.

Exploring the Charge-Trapping Behavior of Self-Assembled Sugar-based Block Copolymers with a Pendent Design in Photoassisted Memory

With unique advantages and features, photonic organic field-effect transistor memory has gained widespread attention over extensive research fields in recent years. In this work, we report the synthesis and device characteristics of three different sugar-based block copolymers, where each contains a pendent maltose (Mal) block and a pendent photoluminescent arene (anthracene (AN), carbazole (CZ), and fluorene (FL)) on a norbornene backbone polymerized through metathesis ring opening polymerization. The corresponding block copolymers are introduced as a polymer electret layer in the photoassisted memory. The hydrophilic maltose block paves the way for self-assembled morphology (ordered vertical cylinder and horizontal cylinder nanostructures) via solvent annealing, while the hydrophobic and photoluminescent arenes act as the charge-trapping site. The optical, electrochemical, and morphological properties were investigated to understand the impact on device performance. The photoassisted memory devices were electrically written by gate bias of −60 V for 1 s and recovered with three kinds of light sources (254-, 365-, and 530 nm lights). Among the studied devices, Mal-b-AN exhibited excellent memory performance with rapid photoresponse owing to the favorable energy levels’ alignment and morphological orientation. Accordingly, the device produced a high memory ratio (>106) over 104 s, a stable performance over 45 endurance cycles, and a wide memory window (∼35 V). This study not only established a detailed explanation of the nanostructures and energy level effect on the memory behaviors of sugar-based block copolymers with a pendent design but also provides an approach for the next-generation optoelectronic devices using green materials.

Ferroelectric polarization-switching acceleration of sputtered Hf0.5Zr0.5O2 with defect-induced polarization of interlayer

Herein, ferroelectric properties of Hf0.5Zr0.5O2 (HZO) are analyzed by inserting various interlayers (ILs) underneath HZO in capacitors and ferroelectric thin-film-transistors (FeTFTs) with all-sputter-deposited metal/HZO/IL/Si (MFIS) stacks. Although all the HZO films have similar phase ratios regardless of the IL, only the MFIS stack with a TiOx IL exhibit polarization switching. To investigate the polarization due to the introduction of TiOx, the polarization of TiOx is checked. It is confirmed that the TiOx can be polarized by the movement of oxygen vacancies (OVs) depending on the electric-field direction, which accelerates the polarization switching of HZO. Therefore, the insertion of the TiOx IL results in a wide (3.4-V) memory window in the FeTFTs, since the IL suppress the leakage current by increasing the IL thickness and simultaneously accelerates the polarization switching of the HZO.

High-Performance Sliding Ferroelectric Transistor Based on Schottky Barrier Tuning

Sliding ferroelectricity associated with interlayer translation is an excellent candidate for ferroelectric device miniaturization. However, the weak polarization gives rise to the poor performance of sliding ferroelectric transistors with a low on/off ratio and a narrow memory window, which restricts its practical application. To address the issue, we propose a facile strategy by regulating the Schottky barrier in sliding ferroelectric semiconductor transistors based on γ-InSe, in which a high performance with a large on/off ratio (106) and a wide memory window (4.5 V) was ultimately acquired. Additionally, the memory window of the device can be further modulated by electrostatic doping or light excitation. These results open up new ways for designing novel ferroelectric devices based on emerging sliding ferroelectricity.

Vertically Stacked Nanosheet FET: Charge- Trapping Memory and Synapse With Linear Weight Adjustability for Neuromorphic Computing Applications

This work shows the feasibility of a vertically stacked nanosheet field effect transistor (NSFET) for charge-trapping memory and artificial synaptic devices. The artificial synapse’s behaviors, long-term potentiation (LTP), and long-term depression (LTD) are analogous to erase (ERS) and program (PGM) of charge-trapping memory, respectively. This NSFET device with a gate length of 50 nm achieves a wider memory window (MW), long retention time for programming, and infinite retention (> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> s) for ERS operation. The results also show linear synaptic features with nonlinearity values of 2.50 and −0.42 for LTP and LTD, respectively. Furthermore, the device conductance values are utilized as synaptic weights for image recognition of Modified National Institute of Standards and Technology (MNIST) dataset in neural networks and achieve 93.30% accuracy. These results make it a promising candidate for next-generation charge-trapping memory and neuromorphic computing due to its wide memory window, long retention, high accuracy, and high density.

Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect Transistors

In this work, we propose a structural approach to mitigate device-to-device variation and performance degradation of ferroelectric (FE) field-effect transistors (FeFETs) due to the inhomogeneity of FE and dielectric (DE) phases of the FE layer. We found that by inserting a floating gate below the FE layer, the polarization effect of FE grains is equalized, thus suppressing the formation of an undesired current percolation path through the channel of the FeFET. This also results in a wider memory window and improved device variation, which ultimately improves the accuracy of in-memory computing. We believe that the proposed approach could be an important strategy enabling reliable and unified operation of FeFETs with the scaling of device.

Air-stable ambipolar charge transport behaviors of organic-inorganic hybrid bilayer and application to Au nanoparticle-based floating gate memory

Ambipolar-based devices are considered effective alternatives in various applications, including reconfigurable logic, light-emitting transistors, and neuromorphic devices. On the other hand, the previously reported intrinsic single-layer ambipolar materials have limitations, such as high instability in ambient air and asymmetric transport of electrons and holes. In the present study, high air-stable and symmetrical ambipolar behavior were implemented using an organic-inorganic bilayer. An ambipolar-based memory application was implemented using these characteristics. This fabricated memory device used electrons and holes together with dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene organic p-type and zinc tin oxide inorganic n-type semiconductor heterojunction layers, resulting in wide memory window and high retention. In addition, these behaviors were analyzed at the band diagram level through ultraviolet photoelectron spectroscopy and ultraviolet-visible light spectroscopy, and chemical bonding was analyzed using x-ray photoelectron spectroscopy. These reports can provide useful strategies for applying various ambipolar applications in the future.

Enhancing the Performance of Electret-Free Phototransistor Memory by Using All-Conjugated Block Copolymer.

Conjugated polymers are of great interest owing to their potential in stretchable electronics to function under complex deformation conditions. To improve the performance of conjugated polymers, various structural designs have been proposed and these conjugated polymers are specially applied in exotic optoelectronics. In this work, a series of all-conjugated block copolymers (PII2T-b-PNDI2T) comprising poly(isoindigo-bithiophene) (PII2T) and poly(naphthalenediimide-bithiophene) (PNDI2T) are developed with varied compositions and applied to electret-free phototransistor memory. Accordingly, these memory devices present p-type transport capability and electrical-ON/photo-OFF memory behavior. The efficacy of the all-conjugated block copolymer design in improving the memory-photoresponse properties in phototransistor memory is revealed. By optimizing the composition of the block copolymer, the corresponding device achieves a wide memory window of 36V and a high memory ratio of 7 × 104 . Collectively, the results of this study indicate a new concept for designing electret-free phototransistor memory by using all-conjugated block copolymer heterojunctions to mitigate the phase separation of conjugated polymer blends. Meanwhile, the intrinsic optoelectronic properties of the constituent conjugated polymers can be well-maintained by using an all-conjugated block copolymer design.

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This study first attempted to fabricate and study the properties of flash memory devices using amorphous In-Ga-sn-O (IGTO) material as a channel material. Compared with devices using amorphous In-Ga-Zn-O (IGZO) material as a channel material, amorphous IGTO flash memory devi ces exhibit improved memory characteristics with faster write/erase speeds (10 µs), improved program/erase (P/E) efficiency, lower sub-threshold swing (SS), higher field effect mobility (µFE) and enhanced on-current to off-current ratio (ION/IOFF). The erasing method and possible mechanism to enhance erasing efficiency utilizing light-assisted negative gate biasing were discussed in this paper. The photo transition is closely related to oxygen vacancy, therefore, the light-assisted approach photo-ionizing oxygen vacancies to generate holes could be a way to achieve erasing under the negative gate bias. Compared with amorphous IGZO thin film, amorphous IGTO thin film has a lower electron affinity and more oxygen vacancies that can provide more holes. In the P/E characterization under different circumstances, amorphous IGTO devices had a wider memory window (MW), and longer retention behaviors. These properties broaden the applications of modern flash device circuits and serve as a reference for future advances in flash storage technology.

Recessed Channel Ferroelectric-Gate Field-Effect Transistor Memory With Ferroelectric Layer Between Dual Metal Gates

In this study, we demonstrate a novel recessed channel ferroelectric field-effect transistor (FeFET) with gate metal/ferroelectric (FE) layer/inter-metal (IM)/interlayer (IL)/Si stacks, which can be called as dual metal gates recessed channel FeFET (DM-RFeFET), for nonvolatile memory applications with high performance and robust reliability. Through technology computer-aided design (TCAD) simulations with calibrated FE and device model parameters, it is revealed that the DM-RFeFET can have the wide memory window (MW) and the possibility of endurance improvement by maximizing the area ratio of FE and IL without sacrificing the footprint. Furthermore, the guidelines for the DM-RFeFET design are provided in terms of recess depth and additional high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> blocking layer between IM and IL to maximize the MW and to minimize IM charging by the gate leakage current.

Photochromic Dithienylethene Monolayer-Modified Gold Nanoparticles as a Tunable Floating Gate in the Fabrication of Nonvolatile Organic Memory.

Nonvolatile memory (NVM) devices were fabricated by implanting a self-assembled monolayer (SAM) of functional dithienylethene (DTE) derivative on the gold nanoparticle (Au-NP) surface in a pentacene-based organic transistor. The Au-NPs and DTE served as a charge-trapping medium and tunneling barrier layer, respectively. The transfer characteristic of the NVM device showed a narrow hysteresis window and wide memory window, indicating that the DTE-SAM served as a variable barrier layer to regulate the trapping and detrapping of external free charges at the Au-NPs. The energy gap introduced by the DTE-SAM is modulated through photoisomerization between a ring-open form and a ring-closed form by absorbing UV or visible light. For a memory device, the ring-closed DTE allows more free charge injection into the trapping sites, and the ring-open one better retains the trapped charges. A longer anchoring alkanethiol chain at the DTE moiety can further extend the device's retention time. For the NVM operation, programming with the ring-closed DTE and then switching the DTE structure to the ring-open form for erasing can facilitate the charge trapping and charge retention with the same molecule compared to operating all in the ring-open form or all in the ring-closed form of DTE. The structural characterization and electronic characteristics of these devices are discussed in detail.

Memory Characteristics of Thin Film Transistor with Catalytic Metal Layer Induced Crystallized Indium-Gallium-Zinc-Oxide (IGZO) Channel

The memory characteristics of a flash memory device using c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) thin film as a channel material were demonstrated. The CAAC-IGZO thin films can replace the current poly-silicon channel, which has reduced mobility because of grain-induced degradation. The CAAC-IGZO thin films were achieved using a tantalum catalyst layer with annealing. A thin film transistor (TFT) with SiO2/Si3N4/Al2O3 and CAAC-IGZO thin films, where Al2O3 was used for the tunneling layer, was evaluated for a flash memory application and compared with a device using an amorphous IGZO (a-IGZO) channel. A source and drain using indium-tin oxide and aluminum were also evaluated for TFT flash memory devices with crystallized and amorphous channel materials. Compared with the a-IGZO device, higher on-current (Ion), improved field effect carrier mobility (μFE), a lower body trap (Nss), a wider memory window (ΔVth), and better retention and endurance characteristics were attained using the CAAC-IGZO device.

Porous p–n junction-induced memory characteristics in low-voltage organic memory transistors

Low-voltage organic memory transistors (LOMTs) as data storage units are crucial for the advancements of future flexible electronics. However, charge storage mechanism remains a great challenge. In this work, we used poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno(3,2-b)thiophene) (PBTTT-C14) as the active layer and incorporated poly(methyl methacrylate) (PMMA) with the PBTTT-C14 through a simple blending process to fabricate LOMTs with porous structure. The function of the porous structure was to improve the carrier traps, which can effectively capture the holes at the charge trapping regions during the programming process. A maximum threshold voltage shift of 1.01 V was achieved when the weight ratio of PBTTT-C14 and PMMA is 7:3, and the LOMTs were operated under the programming process of −4 V/1 s. Impedance-admittance analyses were used to investigate the interfacial trap density of charge trapping regions, which is a supporter of the programming capability of LOMTs. An ultrathin dioctyl perylene tetracarboxylic diimide film was deposited on the active layer with porous structure in LOMTs. This film can increase the carriers’ erasing capability. A wide memory window of 1.64 V was obtained in LOMTs when the devices are operated under the erasing process of bias pulse of 3 V/1 s with the assistance of 2.5 mW cm−2 light irradiation. This study facilitates the development of high-performance LOMT device in fresh-type memory.