Vertically Stacked Nanosheet FET: Charge- Trapping Memory and Synapse With Linear Weight Adjustability for Neuromorphic Computing Applications

Abstract

This work shows the feasibility of a vertically stacked nanosheet field effect transistor (NSFET) for charge-trapping memory and artificial synaptic devices. The artificial synapse’s behaviors, long-term potentiation (LTP), and long-term depression (LTD) are analogous to erase (ERS) and program (PGM) of charge-trapping memory, respectively. This NSFET device with a gate length of 50 nm achieves a wider memory window (MW), long retention time for programming, and infinite retention (> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> s) for ERS operation. The results also show linear synaptic features with nonlinearity values of 2.50 and −0.42 for LTP and LTD, respectively. Furthermore, the device conductance values are utilized as synaptic weights for image recognition of Modified National Institute of Standards and Technology (MNIST) dataset in neural networks and achieve 93.30% accuracy. These results make it a promising candidate for next-generation charge-trapping memory and neuromorphic computing due to its wide memory window, long retention, high accuracy, and high density.