Porous p–n junction-induced memory characteristics in low-voltage organic memory transistors

Abstract

Low-voltage organic memory transistors (LOMTs) as data storage units are crucial for the advancements of future flexible electronics. However, charge storage mechanism remains a great challenge. In this work, we used poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno(3,2-b)thiophene) (PBTTT-C14) as the active layer and incorporated poly(methyl methacrylate) (PMMA) with the PBTTT-C14 through a simple blending process to fabricate LOMTs with porous structure. The function of the porous structure was to improve the carrier traps, which can effectively capture the holes at the charge trapping regions during the programming process. A maximum threshold voltage shift of 1.01 V was achieved when the weight ratio of PBTTT-C14 and PMMA is 7:3, and the LOMTs were operated under the programming process of −4 V/1 s. Impedance-admittance analyses were used to investigate the interfacial trap density of charge trapping regions, which is a supporter of the programming capability of LOMTs. An ultrathin dioctyl perylene tetracarboxylic diimide film was deposited on the active layer with porous structure in LOMTs. This film can increase the carriers’ erasing capability. A wide memory window of 1.64 V was obtained in LOMTs when the devices are operated under the erasing process of bias pulse of 3 V/1 s with the assistance of 2.5 mW cm−2 light irradiation. This study facilitates the development of high-performance LOMT device in fresh-type memory.