Wear Leveling Research Articles

Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory

With the rapid development of technology scaling and cell density improvement for capacity increase and cost reduction, nand flash memory is confronted with degraded reliability. On one hand, while low-density parity-check (LDPC) codes have been deployed in today's nand flash memories to enhance reliability, flash read latency has still been a performance bottleneck with the increased raw bit error rates (RBER). On the other hand, significant process variations (PV) have been found on existing nand flash memories, which introduce great reliability variations among different flash blocks. Recent studies have proposed to exploit PV to improve endurance by better wear leveling or to improve write performance. These approaches are prone to allocate read data to blocks with low reliability, which further degrades read performance. This paper proposes to enhance read performance of LDPC-equipped nand flash memory by exploiting the reliability variations from PV. The paper consists of three parts. First, a block grouping approach is presented to categorize flash blocks according to their reliability. Second, according to the grouping scheme, a data placement scheme is proposed, which allocates read-hot data to flash blocks with high reliability. At the same time, the read-cold data is moved to blocks with low reliability. As a result, the read performance is enhanced. However, allocating high reliable blocks for read-hot data collides with previous PV-based wear leveling methods. To address the issue, the third part is a grouping partition scheme which limits the amount of high reliable blocks occupied by read-hot data. Therefore, read performance enhancement can be achieved and the wear leveling schemes will be impacted slightly. Experiment results present that, the proposed approach can provide significant read performance improvement on LDPC-equipped nand flash memory and is compatible with the previous PV-based wear leveling.

An Efficient and Non-Time-Sensitive File-Aware Garbage Collection Algorithm for NAND Flash-Based Consumer Electronics

NAND flash memory has been widely used in consumer electronics, such as tablet personal computers and smart phones. However, unlike traditional hard disk, a garbage collection is required to reclaim memory space during data updates. A garbage collection includes a series of extra read, write and erase operations. Both write and erase operations are time consuming process, which affect the effectiveness and efficiency of the NAND flash memory system. Moreover, flash memory blocks are challenged by the limitation of the erase count. Thus, considerable efforts have been paid to reduce the garbage collection overhead and improve wear leveling. In this paper, an efficient and non-time-sensitive file-aware garbage collection algorithm, called FaGC+, is proposed. The FaGC+ algorithm involves a novel update frequency calculation method and a novel cold-hot logical page categorization scheme. The experimental results demonstrate that the proposed algorithm outperforms existing garbage collection algorithms in terms of garbage collection overhead and time-sensitivity in wear leveling control.

Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD

Hybrid solid state drive based on ReRAM and NAND flash technologies has shown promising performance and energy efficiency. In this application, ReRAM is mainly used as a non-volatile buffer to hold recently accessed data pages or address mapping information. The previous studies on the ReRAM-based buffer mainly focus on performance and efficiency improvement, while reliability issues are not taken into consideration. Nevertheless, according to our quantitative evaluation, the limited endurance and random bit errors pose challenges to ReRAM-based buffer design. For example, without wear leveling, the raw lifetime of ReRAM-based SSD buffer may be as low as 0.02 year for some specific I/O traces. Therefore, we propose two efficient architecture techniques, i.e., multi-bloom-filter-based wear leveling and hybrid error protection, to improve the lifetime and reduce the error protection cost of ReRAM-based buffer, respectively. Simulation results demonstrate that the proposed wear leveling technique can extend the lifetime of ReRAM-based buffer by $34.7\times $ on average. The proposed hybrid error protection scheme can improve the response time by at least 4.2% compared with other error protection schemes.

Management of Next-Generation NAND Flash to Achieve Enterprise-Level Endurance and Latency Targets

Despite its widespread use in consumer devices and enterprise storage systems, NAND flash faces a growing number of challenges. While technology advances have helped to increase the storage density and reduce costs, they have also led to reduced endurance and larger block variations, which cannot be compensated solely by stronger ECC or read-retry schemes but have to be addressed holistically. Our goal is to enable low-cost NAND flash in enterprise storage for cost efficiency. We present novel flash-management approaches that reduce write amplification, achieve better wear leveling, and enhance endurance without sacrificing performance. We introduce block calibration, a technique to determine optimal read-threshold voltage levels that minimize error rates, and novel garbage-collection as well as data-placement schemes that alleviate the effects of block health variability and show how these techniques complement one another and thereby achieve enterprise storage requirements. By combining the proposed schemes, we improve endurance by up to 15× compared to the baseline endurance of NAND flash without using a stronger ECC scheme. The flash-management algorithms presented herein were designed and implemented in simulators, hardware test platforms, and eventually in the flash controllers of production enterprise all-flash arrays. Their effectiveness has been validated across thousands of customer deployments since 2015.

RETROFIT: Fault-Aware Wear Leveling

Phase-change memory (PCM) and resistive memory (RRAM) are promising alternatives to traditional memory technologies. However, both PCM and RRAM suffer from limited write endurance and due to process variation from scaling, increasing number of early cell failures continue to put pressure on wear-leveling and fault tolerance techniques. In this paper, we propose RETROFIT, which leverages the spare “gap” row used as temporary storage in wear leveling to also be used strategically to guard against early cell wear out. RETROFIT is compatible with error correction schemes targeted at mitigating stuck-at faults and provides benefits when single or multiple spare rows are available. RETROFIT enhances lifetime by as much as 107 percent over traditional gap-based wear leveling and 8 percent over perfectly uniform wear leveling with a similar overhead. Furthermore, RETROFIT scales better than wear-leveling combined with error correction as process variation increases.

Enhancing security of NVM-based main memory with dynamic Feistel network mapping

As promising alternatives in building future main memory systems, emerging non-volatile memory (NVM) technologies can increase memory capacity in a cost-effective and power-efficient way. However, NVM is facing security threats due to its limited write endurance: a malicious adversary can wear out the cells and cause the NVM system to fail quickly. To address this issue, several wear-leveling schemes have been proposed to evenly distribute write traffic in a security-aware manner. In this study, we present a new type of timing attack, remapping timing attack (RTA), based on information leakage from the remapping latency difference in NVM. Our analysis and experimental results show that RTA can cause three of the latest wear-leveling schemes (i.e., region-based start-gap, security refresh, and multi-way wear leveling) to lose their effectiveness in several days (even minutes), causing failure of NVM. To defend against such an attack, we further propose a novel wear-leveling scheme called the ‘security region-based start-gap (security RBSG)’, which is a two-stage strategy using a dynamic Feistel network to enhance the simple start-gap wear leveling with level-adjustable security assurance. The theoretical analysis and evaluation results show that the proposed security RBSG not only performs well when facing traditional malicious attacks, but also better defends against RTA.

Improvement of Garbage Management for NAND Memory System

<p>Recent days increasing the use of flash memory device in embedded systems. Diverse qualities of NAND blaze recollections from hard circles include: a constrained square eradicate check, the inconceivability of set up refresh, and asymmetry in operation granularity. Along these lines different rubbish accumulation procedures for the NAND streak recollections have been proposed. In any case, existing rubbish accumulation procedures obstruct square wear leveling since they utilize a similar technique for both hot and icy information. In this paper, we propose effective junk accumulation and piece administration strategies to enhance piece wear leveling and trash gathering speed. Above all else, information is arranged into three sorts concurring to alteration recurrence - hot information, cool information, and warm data and distinctive sorts of information are put away in various pieces. The delete cost is figured considering information sort, and afterward junk gathering is performed for the hinders whose eradicate costs surpass the limit esteem. Furthermore, unique square records are made in RAM by information sort, and the squares are orchestrated in the request of their eradicate cost.</p>

Dynamic Virtual Page-Based Flash Translation Layer With Novel Hot Data Identification and Adaptive Parallelism Management

Solid-state disks (SSDs) tend to replace traditional motor-driven hard disks in high-end storage devices in past few decades. However, various inherent features, such as out-of-place update [resorting to garbage collection (GC)] and limited endurance (resorting to wear leveling), need to be reduced to a large extent before that day comes. Both the GC and wear leveling fundamentally depend on hot data identification (HDI). In this paper, we propose a hot data-aware flash translation layer architecture based on a dynamic virtual page (DVPFTL) so as to improve the performance and lifetime of NAND flash devices. First, we develop a generalized dual layer HDI (DL-HDI) framework, which is composed of a cold data pre-classifier and a hot data post-identifier. Those can efficiently follow the frequency and recency of information access. Then, we design an adaptive parallelism manager (APM) to assign the clustered data chunks to distinct resident blocks in the SSD so as to prolong its endurance. Finally, the experimental results from our realized SSD prototype indicate that the DVPFTL scheme has reliably improved the parallelizability and endurance of NAND flash devices with improved GC-costs, compared with related works.

Wear Leveling for Non-Volatile Memory: a Runtime System Approach

Recent advances in non-volatile memory (NVM) technology offer more capacity, scalability, and durability than regular volatile memory. However, adopting emerging memory introduces new challenges such as endurance issue and performance degradation. This paper proposes a software wear leveling technique that is designed specifically for a scenario, where the NVM is managed by generational garbage collectors that divide heap into separate young and old space. Prior work found that the majority of write traffic occurs to young generation heap, thus proposed a hybrid generational heap, where the NVM is utilized as old space and DRAM works as young space. We further investigate the access pattern in NVM-contained old generation. This paper first highlights a common observation across various workloads that the write distribution of old space is highly unbalanced. Specifically, among all writes to the NVM, 56%–96% occurs to 2% memory pages, and in worst cases, 83%–96% traffic occurs to only 0.5% pages. This leveling can be achieved by only swapping a very small fraction of NVM pages during the garbage collection cycle, which makes a low performance overhead runtime approach possible. We maintain a write intensity counter for each thread and insert a new garbage collection phase, where a few hottest pages are selected and remapped. Results show our approach significantly mitigates the skewness indicated by Gini coefficient dropping from 0.95 to 0.60, leading to extending lifetime 41 times on average. Meanwhile, it incurs a performance cost of 7.2% longer mutation time measured on emulated memory without performance penalty, and 3.31 % extra stop time for garbage collection cycles.

Ouroboros Wear Leveling for NVRAM Using Hierarchical Block Migration

Emerging nonvolatile RAM (NVRAM) technologies have a limit on the number of writes that can be made to any cell, similar to the erasure limits in NAND Flash. This motivates the need for wear leveling techniques to distribute the writes evenly among the cells. Unlike NAND Flash, cells in NVRAM can be rewritten without the need for erasing the entire containing block, avoiding the issues of space reclamation and garbage collection, motivating alternate approaches to the problem. In this article, we propose a hierarchical wear-leveling model called Ouroboros wear leveling. Ouroboros uses a two-level strategy whereby frequent low-cost intraregion wear leveling at small granularity is combined with interregion wear leveling at a larger time interval and granularity. Ouroboros is a hybrid migration scheme that exploits correct demand predictions in making better wear-leveling decisions while using randomization to avoid wear-leveling attacks by deterministic access patterns. We also propose a way to optimize wear-leveling parameter settings to meet a target smoothness level under limited time and space overhead constraints for different memory architectures and trace characteristics. Several experiments are performed on synthetically generated memory traces with special characteristics, two block-level storage traces, and two memory-line-level memory traces. The results show that Ouroboros wear leveling can distribute writes smoothly across the whole NVRAM with no more than 0.2% space overhead and 0.52% time overhead for a 512GB memory.

Building NVRAM-Aware Swapping Through Code Migration in Mobile Devices

Mobile applications are becoming increasingly feature-rich and powerful, but also dependent on large main memories, which consume a large portion of system energy, especially for devices equipped with 4/6 GB DRAM. Swapping inactive DRAM pages to byte-addressable, non-volatile memory (NVRAM) is a promising solution to this problem. However, most NVRAMs have limited write endurance and the current victim pages selecting algorithm does not aware it. Therefore, to make it practical, the design of an NVRAM based swapping system must also consider endurance. In this paper, we target at prolonging the lifetime of NVRAM based swap area in mobile devices by reducing the write activities to NVRAM based swap area. Different from traditional wisdom, such as wear leveling and hot/cold data identification, we propose to build a system called n Code, which exploits the fact that code pages are easy to identify, read-only, and therefore a perfect candidate for swapping. Utilizing NVRAM’s byte-addressability, we support execute-in-place (XIP) of the code pages in the swap area, without copying them back to DRAM based main memory. Experimental results based on the Google Nexus 5 smartphone show that n Code can effectively prolong the lifetime of NVRAM under various workloads.

Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs

Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear leveling induced read, write, and erase operations, to solve the issues of inability of in-place updates and limited lifetime. When internal activities are triggered on a chip, the chip will be blocked. Our preliminary studies on several workloads show that when internal activities are frequently triggered, the host I/O performance will be significantly impacted because of the access conflict between them. In this work, in order to improve the access conflict induced performance degradation, a novel access conflict minimization scheme is proposed. The basic idea of the scheme is motivated by an interesting observation in SSDs: several chips are idle when other chips are busy with internal activities and host I/O requests. Based on this observation, we propose to schedule internal activities induced operations for minimized access conflict by exploiting the idleness of the multiple chips of SSDs. This approach is realized by two steps: First, read internal activities accessed data to the controller; second, by exploiting the idle chips during internal activities, write internal activities accessed data back to these idle chips. With this scheme, the internal activities can be processed with minimized access conflict to the host requests. Simulation results show that the proposed approach significantly reduces the access conflict, and in turn leads to a significant performance improvement of SSDs.

HALO: a fast and durable disk write cache using phase change memory

To close the increasing performance gap between disk storage and processors, flash based solid-state devices (FSSDs) have been adopted within the memory hierarchy to improve the performance of hard disk drive (HDD) based storage system. However, FSSDs still suffer from erase-before-write restriction, coarse access granularity and limited write endurance. Recently, the cutting-edge non-volatile memory technologies are merging, e.g., phase-change memory and resistive memory, which offer us new storage alternatives with faster access, byte-addressability and better endurance. In order to address the imperative data intensive computing issues, we propose to leverage PCM as disk write cache for constructing a hybrid PCM+HDD storage architecture in this paper. First, we develop a novel hash-based write caching scheme called HALO to improve both spatial and temporal locality on hard disks, thus addressing the limitations of traditional LRU caching algorithms and rendering better I/O performance. To deal with the limited durability of PCM devices and reclaim the degraded spatial locality in previous wear-leveling techniques, we further propose novel PCM wear leveling algorithms that provide effectively uniform writes while maximizing access parallelism. We have evaluated this PCM-based hybrid storage architecture using applications with a diverse set of I/O access patterns. Our experimental results demonstrate that the HALO caching scheme leads to an average reduction of 36.8% in execution time compared to the LRU caching scheme, and that the space filling curve based wear leveling extends the lifetime of PCM by a factor of 21.6.

Harmonized memory system for object-based cloud storage

A new storage system that integrates non-volatile with conventional memory, a harmonized memory system (HMS) for object-based cloud storage, is proposed. The system overcomes IO bottlenecks when managing large amounts of metadata and transaction logs and is composed of five modules. The first, the harmonized memory supervisor, is a translation layer for accessing the harmonized array module. It manages address translation, address mapping by page linking, and wear leveling. The second, the harmonized array module, is divided into dynamic and static areas composed of DRAM, and PCM together with NAND flash memory, respectively. The harmonized memory migration engine and data pattern predictor, which anticipates future data flow, are designed to maximize the effectiveness of the PCM array area. The harmonized logging conductor processes the log between the PCM array and NAND flash areas. Experimental results show the total execution time and energy consumption of HMS is 5.77 faster and 4.27 times lower, respectively, than the conventional DRAM-HDD model for object-based storage workloads.

Exploiting Multiple Write Modes of Nonvolatile Main Memory in Embedded Systems

Existing Nonvolatile Memories (NVMs) have many attractive features to be the main memory of embedded systems. These features include low power, high density, and better scalability. Recently, Multilevel Cell (MLC) NVM has gained more and more popularity as it can provide a higher density than the traditional Single-Level Cell (SLC) NVM. However, there are also drawbacks in MLC NVM, namely, limited write endurance and expensive write operation. These two drawbacks have to be overcome before MLC NVM can be practically adopted as the main memory. In MLC Nonvolatile Main Memory (NVMM), two different types of write operations with very diverse data retention times are allowed. The first type maintains data for years but takes a longer time to write and is detrimental to the endurance. The second type maintains data for a short period but takes a shorter time to write. By observing that much of the data written to main memory is temporary and does not need to last long during the execution of a program, in this article, we propose novel task scheduling and write operation selection algorithms to improve MLC NVMM endurance and program efficiency. An Integer Linear Programming (ILP) formulation is first proposed to obtain optimal results. Since ILP takes exponential time to solve, we also propose the Multiwrite Mode-Aware Scheduling (MMAS) algorithm to achieve a near-optimal solution in polynomial time. Additionally, the Dynamical Memory Block Screening (DMS) algorithm is proposed to achieve wear leveling. The experimental results demonstrate that the proposed techniques can greatly improve the lifetime of the MLC NVMM as well as the efficiency of the program.

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.

Hot Data Identification For Flash Based Storage Systems Considering Continuous Write Operation

Recently, NAND flash memory, which is used as a storage medium, is replacing HDD (Hard Disk Drive) at a high speed due to various advantages such as fast access speed, low power, and easy portability. In order to apply NAND flash memory to a computer system, a Flash Translation Layer (FTL) is indispensably required. FTL provides a number of features such as address mapping, garbage collection, wear leveling, and hot data identification. In particular, hot data identification is an algorithm that identifies specific pages where data updates frequently occur. Hot data identification helps to improve overall performance by identifying and managing hot data separately. MHF (Multi hash framework) technique, known as hot data identification technique, records the number of write operations in memory. The recorded value is evaluated and judged as hot data. However, the method of counting the number of times in a write request is not enough to judge a page as a hot data page. In this paper, we propose hot data identification which considers not only the number of write requests but also the persistence of write requests.

Postcycling Degradation in Metal-Oxide Bipolar Resistive Switching Memory

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage $V_{\mathrm{ set}}$ , the reset voltage $V_{\mathrm{ reset}}$ , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array.

Performance and reliability concern scheme for efficient garbage collection and wear leveling on flash memory-based solid state disk

In the near future, data is expected to double in every two years, which translates to more than one terabyte of data for every person on earth. The difficulty of storing and fetching required data from data centers and servers will consequently increase. As a result, significant attention has been given to the flash memory-based solid state drive (SSD) from consumer electronics companies, which has begun to replace the existing hard disk drive and is highly likely to be used as a storage unit for most of consumer electronics to achieve low power consumption. In contrast to traditional disk, SSD uses semiconductor chips to store data. This structure enjoys original technical characteristics, including low power consumption, shock resistance, and high performance in random access. Such features can overcome the shortcomings of magnetic disks. However, flash memory, the basic unit of SSD, has many distinctive characteristics that cause various challenges. Flash memory does not support updating in the place method. A write operation can be performed only on an empty or erased unit, making the process more time-consuming. Moreover, each storage unit has a limited number of erase cycles, after which the block becomes invalid. This research proposes a new scheme called performance and reliability concern to increase the reliability and performance of SSDs. The eligibility of the proposed scheme is proven through EagleTree simulator. The scheme is also compared with other state-of-the-art techniques in terms of effectiveness and efficiency. Experimental results show that the proposed scheme provides sufficient performance and reliability for SSD.

Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory

Recently, phase change memory (PCM) has become a promising candidate to replace dynamic RAM as main memory due to its low power consumption, fast I/O performance, and byte addressability. Accompanied with the merits, the adoption of PCM may suffer from its physical characteristic of limited write endurance. Wear leveling is a well-known approach to address this issue. For PCM main memory, the design of wear leveling should stress operation efficiency and overhead reduction. Nevertheless, conventional designs are usually dedicated to prolonging the lifetime of PCM in the best effort. In this paper, we propose a novel perspective that, instead of valuing PCM lifetime exploitation as the first priority, we turn to satisfy the product warranty period. With such a paradigm shift, the management overhead of wear-leveling mechanisms could be reduced so as to achieve further enhancement of operation efficiency. To this end, we propose a warranty-aware page management design that introduces novel criteria used to determine the state of a page by taking both the product warranty period and the write cycles of a page into consideration. Theoretical analysis is also conducted to investigate the properties and performance of the proposed management. To show the effectiveness of the proposed design, we collected real traces by running SPEC2006 benchmarks with different write intensity workloads. The experimental results showed that our design reduced the overhead to one-third that of the state-of-the-art designs while still providing the same level of performance.