Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD

Abstract

Hybrid solid state drive based on ReRAM and NAND flash technologies has shown promising performance and energy efficiency. In this application, ReRAM is mainly used as a non-volatile buffer to hold recently accessed data pages or address mapping information. The previous studies on the ReRAM-based buffer mainly focus on performance and efficiency improvement, while reliability issues are not taken into consideration. Nevertheless, according to our quantitative evaluation, the limited endurance and random bit errors pose challenges to ReRAM-based buffer design. For example, without wear leveling, the raw lifetime of ReRAM-based SSD buffer may be as low as 0.02 year for some specific I/O traces. Therefore, we propose two efficient architecture techniques, i.e., multi-bloom-filter-based wear leveling and hybrid error protection, to improve the lifetime and reduce the error protection cost of ReRAM-based buffer, respectively. Simulation results demonstrate that the proposed wear leveling technique can extend the lifetime of ReRAM-based buffer by $34.7\times $ on average. The proposed hybrid error protection scheme can improve the response time by at least 4.2% compared with other error protection schemes.