Postcycling Degradation in Metal-Oxide Bipolar Resistive Switching Memory

Zhongqiang Wang,Nirmal Ramaswamy,Scott Sills,Stefano Ambrogio,Daniele Ielmini,Simone Balatti,Alessandro Calderoni

doi:10.1109/ted.2016.2604370

Abstract

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage $V_{\mathrm{ set}}$ , the reset voltage $V_{\mathrm{ reset}}$ , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array.

Highlights

R ESISTIVE switching memory (RRAM) attracts broad interests due to the high-speed operation [1], low-power consumption [2], [3], and nonvolatile retention [4], serving as a promising candidate for storage-class memory [5] and embedded nonvolatile memory [6]
It was shown that the endurance failure of bipolar RRAM is Manuscript received April 23, 2016; revised July 9, 2016 and August 4, 2016; accepted August 26, 2016
This paper studies the cycling-induced degradation of HfO2 RRAM device arranged in a one-transistor/one-resistor (1T1R) structure

Summary

INTRODUCTION

R ESISTIVE switching memory (RRAM) attracts broad interests due to the high-speed operation [1], low-power consumption [2], [3], and nonvolatile retention [4], serving as a promising candidate for storage-class memory [5] and embedded nonvolatile memory [6]. This paper studies the cycling-induced degradation of HfO2 RRAM device arranged in a one-transistor/one-resistor (1T1R) structure. We show that the cycling degradation leads to a decrease of several RRAM parameters, such as the resistance of the low-resistance state (LRS), the set voltage Vset, the reset voltage Vreset, and the corner voltage Vcorner, defined as the voltage for which the switching speed becomes comparable with the inherent RC delay time in the 1T1R structure. We evidence and support the capability to monitor degradation by tracking the reset voltage Vreset or the LRS resistance R. This methodology may enable stress-aware methods to predict and anticipate device failure in the memory array

EXPERIMENTAL SAMPLES AND SETUP

DEPENDENCE ON THE NUMBER OF CYCLES

PHYSICAL INTERPRETATION AND MODEL

DEPENDENCE ON Vstop

MODELING OF Vstop-DEPENDENT DEGRADATION

VIII. CONCLUSION