Wear Leveling Research Articles

MFGC: Minimal First Garbage Collection for Monitoring of Context-Aware Victim Selection

SSDs based on NAND flash are becoming a feasible secondary storage option for many computer systems. Because NAND flash memory is dif- ferent from regular HDDs, flash-based SSDs frequently have an interface layer known as Flash Translation Layer (FTL). Garbage collection tech- nique is required to free up space. Garbage collection policy is primarily concerned with cleaning costs and wear-leveling. To achieve the above design principles, we have proposed an effective minimal first garbage col- lection termed as MFGC. MFGC manages the blocks in the list, sorted in descending order of erase count. This list is divided into two regions: preference region and alternate region. The adaptive window for victim selection is used, which adapts dynamically as the cleaning cost changes. After the victim selection, effective data identification of valid hot page and valid cold page is done based on threshold and redistribution of them is done to free blocks. A Series of trace simulations is performed to evaluate the performance of proposed approach with other existing approaches. MFGC outperforms GR, CB, CAT, CATA and MCSGC by 85.5%, 77.1%,61.7%, 56.7% and 43.5% respectively.The outcome of the simulation demonstrates that our approach is superior to others in terms of erase and copy operations as well as wear leveling of blocks.

MFGC: Minimal First Garbage Collection for Monitoring of Context-Aware Victim Selection

SSDs based on NAND flash are becoming a feasible secondary storage option for many computer systems. Because NAND flash memory is dif- ferent from regular HDDs, flash-based SSDs frequently have an interface layer known as Flash Translation Layer (FTL). Garbage collection tech- nique is required to free up space. Garbage collection policy is primarily concerned with cleaning costs and wear-leveling. To achieve the above design principles, we have proposed an effective minimal first garbage col- lection termed as MFGC. MFGC manages the blocks in the list, sorted in descending order of erase count. This list is divided into two regions: preference region and alternate region. The adaptive window for victim selection is used, which adapts dynamically as the cleaning cost changes. After the victim selection, effective data identification of valid hot page and valid cold page is done based on threshold and redistribution of them is done to free blocks. A Series of trace simulations is performed to evaluate the performance of proposed approach with other existing approaches. MFGC outperforms GR, CB, CAT, CATA and MCSGC by 85.5%, 77.1%,61.7%, 56.7% and 43.5% respectively.The outcome of the simulation demonstrates that our approach is superior to others in terms of erase and copy operations as well as wear leveling of blocks

SSD DISCORE - A SCORING METHOD FOR SSD'S DATA INTEGRITY VALIDATION USING DIFFERENT SMART ATTRIBUTES IN THE DIGITAL FORENSICS PROCESS

Solid-state drives (SSD) are replacing hard disk drives (HDD) in the majority of computer systems today. Because SSDs outperform HDDs in terms of efficiency, SSDs are now more necessary to replace HDDs. However, due to uncertain data integrity, SSDs are not forensically sound in design. The data on SSD is continuously changing as a result of Wear Leveling, TRIM and Garbage Collection, which makes data integrity verification in digital forensics challenging. The use of hash algorithms to validate data integrity is crucial in establishing the legitimacy of evidence gathered from suspect systems. In order to shed light on this matter, an experiment was carried out to gather data from an SSD in both user active and user non-active state. The data was then analyzed using the different attributes of Self-Monitoring, Analysis, and Reporting Technology (SMART) to ascertain the data integrity and by proposing a scoring method “SSD DiScore (SSD Data Integrity Score)”, which can aid in digital forensic investigation procedure.

A Scalable Wear Leveling Technique for Phase Change Memory

Phase Change Memory (PCM), one of the recently proposed non-volatile memory technologies, has been suffering from low write endurance. For example, a single-layer PCM cell could only be written approximately 10 8 . This limits the lifetime of a PCM-based memory to a few days rather than years when memory-intensive applications are running. Wear leveling techniques have been proposed to improve the write endurance of a PCM. Among those techniques, the region-based start-gap (RBSG) scheme is widely cited as achieving the highest lifetime. Based on our experiments, RBSG can achieve 97% of the ideal lifetime, but only for relatively small memory sizes (e.g., 8–32GB). As the memory size goes up, RBSG becomes less effective and its expected percentage of the ideal lifetime reduces to less than 57% for a 2TB PCM. In this article, we propose a table-based wear leveling scheme called block grouping to enhance the write endurance of a PCM with a negligible overhead. Our research results show that with a proper configuration and adoption of partial writes (writing back only 64B subblocks instead of a whole row to the PCM arrays) and internal row shift (shifting the subblocks in a row periodically so no subblock in a row will be written repeatedly), the proposed block grouping scheme could achieve 95% of the ideal lifetime on average for the Rodinia, NPB, and SPEC benchmarks with less than 1.74% performance overhead and up to 0.18% hardware overhead. Moreover, our scheme is scalable and achieves the same percentage of ideal lifetime for PCM of size from 8GB to 2TB. We also show that the proposed scheme can better tolerate memory write attacks than WoLFRaM (Wear Leveling and Fault Tolerance for Resistive Memories) and RBSG for a PCM of size 32GB or higher. Finally, we integrate an error-correcting pointer technique into our proposed block grouping scheme to make the PCM fault tolerant against hard errors.

Flash storage technology status and development research

Data storage devices are an important component of computer systems. Solid-state Drives, which use NAND Flash technology, are widely used in various fields due to their unique advantages such as high read-write speed, low power consumption, shock resistance, and small size compared to traditional mechanical hard drives. This paper first discusses the basic structure and principles of Flash memory, including floating gate transistors for storing and reading charges. Based on the current state of NAND Flash-based solid-state hard drives, this paper discusses key technologies and characteristics such as flash memory types, wear leveling, garbage collection, etc. It explores their features, advantages and limitations, and finally reasonably deduces the future development trend of Flash devices.

Effective Stack Wear Leveling for NVM

With the rapid growth of data processed by computer systems, Non-Volatile Memory (NVM), represented by Phase Change Memory (PCM), is regarded as a promising nextgeneration storage technology as it offers superior advantages over DRAM. However, PCM suffers from a severe write durability problem, leading to an extremely short lifespan under the uneven write patterns of real-world programs. We observe that loops are one of the primary causes of uneven writes on the stack. To alleviate this problem, we present Loop2Recursion, a compiler-assisted stack wear leveling technique that automatically transforms loops into recursive functions. In addition, we propose several optimizations to reduce the stack sizes and instruction counts of the generated recursive functions, two schemes to limit recursion depth, and selective loop transformation for cache-enabled architectures. Experimental results demonstrate that Loop2Recursion outperforms state-of-the-art methods by significantly improving stack wear leveling with a greatly reduced performance overhead.

An Efficient Hot-Cold Data Separation Garbage Collection Algorithm Based on Logical Interval in NAND Flash-Based Consumer Electronics

In NAND flash-based consumer electronics, garbage collection can degrade consumer electronics performance. And the extra page writes caused by garbage collection reduce the lifespan of consumer electronics. Hot-cold data separation has a critical impact on garbage collection. Therefore, inaccurate hot-cold data separation significantly affects garbage collection overhead and the performance of wear leveling. In addition, accurate data separation depends greatly on heat calculation of each page in NAND flash and extra memory is required to record page heat information. In this paper, we propose an efficient and novel hot-cold data separation garbage collection algorithm. The proposed algorithm introduces T-P factor which combines update time and page sequence number to calculate the heat of different logical interval rather than page, thus accurate hot-cold data separation can be achieved. Based on T-P factor, garbage collection strategy is improved accordingly. Experimental results show that the proposed algorithm is superior to existing algorithms in terms of garbage collection overhead, wear leveling and extra memory consumption in NAND flash-based consumer electronics.

On the Cost of Near-Perfect Wear Leveling in Flash-Based SSDs

Wear leveling (WL) techniques in flash-based SSDs aim at distributing the erase cycles as uniformly as possible across the memory blocks within the SSD to extend its life span. The downside of any WL technique is that it causes additional internal write operations, thereby increasing the so-called write amplification (WA) factor, which equals the ratio between the total number of writes performed and the number of writes requested by the host system. In this article, we address the question whether near-perfect WL is possible at low costs in terms of the WA factor. We answer this question affirmatively by presenting a simple randomized algorithm that combines WL with garbage collection. This algorithm guarantees that the wear is nearly perfectly balanced at all times while causing a low increase in the WA. This is demonstrated mathematically using a mean field model in case of uniform random writes and using trace-driven simulation experiments for general workloads.

Enhancing the lifetime of STT-RAM using compression based wear leveling technique

Driven memory requirements have increased with the increase in processor core count and working sets. Conventional memory technology such as SRAM (static random access memory) is unable to fulfill these demands. Alternate memory technologies such as NVM (non-volatile memory) have been proposed to fulfill the demands of higher memory usage due to its huge storage capacity and less leakage power. Though NVM is having the above advantages, it is limited in performance due to write restrictions. The write restriction directly affects the cache lifetime, which is an important parameter for computer system performance. This paper explores a compression based wear leveling technique to overcome the limitations of write restriction and to improve the cache lifetime. The proposed method lessens the bit writes to be written and also distributes the write equally in the sets of the cache. The frequent pattern compression is used to reduce each word write based on defined pattern sets. The writes are spread within word to enable uniform distribution of writes. The bit transitions during the writes can be reduced further by identifying the existing cache line with minimum transitions to be placed. Wear leveling is implemented to enhance the cache endurance by equally distributing the incoming writes to all the cache blocks. The proposed method improves the lifespan by 42 %, 52 %, 75 % and 18 % with a 5 % area overhead compared to LER, TA_LRU, Equalwrites and Compression+EW techniques.

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime.

Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.

Adaptive Switch on Wear Leveling for Enhancing I/O Latency and Lifetime of High-Density SSDs

NAND flash-based high-density solid-state drives (SSDs) commonly have limited write endurance, as a single block becomes unavailable after a finite number of program/erase cycles. The (static) wear leveling algorithms migrate cold data to more worn blocks for yielding an even distribution of wears in SSDs. However, migrating cold data must delay normal I/O processing, and unnecessary wear leveling operations may damage SSD endurance as each operation causes a program/erase cycle. This article proposes an adaptive switch on wear leveling (called ASWL), to boost I/O performance and lifetime for high-density SSDs. The basic idea of ASWL is to adaptively switch the threshold function for intelligently triggering wear leveling operations at different stages of SSD lifetime. To this end, we build a mathematical model determining the wear leveling threshold condition with a dynamic manner, by considering the real-time factors of I/O intensity and the wear difference of SSD blocks. Through a series of emulation experiments on several realistic disk traces, we show that the proposed ASWL mechanism can not only greatly improve I/O performance but also noticeably extend the lifetime of high-density SSDs, in contrast to existing wear leveling methods.

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.03\times $ </tex-math></inline-formula> , at cost of 12.5% storage overhead.

Score Based Garbage Collection Algorithm for Flash Based Storage System

A solid-state drive’s garbage collection technique considerably influences the drive’s writing performance and life duration. The garbage collection technique chooses the block to be erased so that the block can be reused. Several techniques, such as hot data identification, enhance the efficiency of garbage collection and impact flash memory access speed and lifespan. This paper proposes a garbage collection algorithm, SGC (Score-based Garbage Collection) which tries to identify data on the basis of threshold into hot and cold blocks then the process is followed by choosing victim block with the help of score for garbage collection. The SGC approach minimises SSD wear frequency and garbage collection overhead, extending SSD life and data reliability. A novel hot and cold identification system helps to reduces program/erasure cycles while increasing identification accuracy, basedon threshold data are clustered into hot and cold. The experimental findings illustrate that the SGC outperforms the existing approach under various benchmarks by reducing the frequency of block wear leveling. The simulation result shows how SGC performs well and lowers the costs, such as the number of copy and erase operation done, wear on the block, and energy consumption.Improvement percentage for wear leveling is calculated for input traces exchange, financial 1 and financial 2. For exchange trace our policy outperforms CB,CAT,GR and CATA by 19.04%,15.0%,37.03% and 10.5% respectively.

Gray counters for non-volatile memories

New technologies for non-volatile memories combine the speed and byte addressability of current memory technologies with the low cost, density, and non-volatility of current storage technologies. They use energy only when writing or reading data. While some newer technologies have practically unlimited endurance, others, such as Phase Change Memory do not. However, this limited endurance surpasses that of solid state drives by several orders of magnitude. They can be integrated into the current memory storage hierarchy as a replacement for DRAM. To manage limited endurance, age-based wear leveling divides the memory into pages and counts the number of writes to a page. Pages with high counts can then be relegated to store more stable data. Counters experience “write concentration” as they are incremented as frequently as a page is written, but the changes are concentrated in a much smaller area around the least significant bit. Current designs store page write counters with the page table in the main memory unit.We propose and investigate an alternative counter design based on Gray codes that distributes the bit-flips resulting from the increments over the vast majority of the bits making up the counter. This is a bit-flip aware data structure that can be used in other contexts as well. We show that this design allows us to integrate the page counters into the phase change memory device. We also investigate counters using error control codes.

Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs

Static random access memory (SRAM) based field-programmable gate array (FPGA) is currently facing challenges of high leakage power and limited capacity. Replacing SRAM in FPGA with emerging nonvolatile memory (NVM) has become an effective way to solve this issue. While enjoying the advantages of NVM in power consumption and integration, nonvolatile FPGA platform is also plagued by lifetime problem. Among all components, block random access memory (BRAM) has the severest endurance problem. The state-of-the-art wear leveling strategies for NVM-based BRAMs rely heavily on static analysis. However, the static analysis would not be accurate enough for application with multiple runtime working patterns. In this article, we propose a pattern-aware wear leveling mechanism. It can improve lifetime through adaptive reconfiguration without static analysis. Evaluation shows that our mechanism can achieve 120% higher lifetime improvement with 4% performance overhead than existing performance-aware wear leveling strategy (Huai et al., 2019).

WDBT: Non-volatile memory wear characterization and mitigation for DBT systems

Emerging high-capacity and byte-addressable non-volatile memory (NVM) is promising for the next-generation memory system. However, NVM suffers from limited write endurance, as an NVM cell will wear out very soon after a certain number of writes, making NVM undependable. To address this issue, many wear reduction and leveling mechanisms have been proposed. Nevertheless, most of these mechanisms are developed without the knowledge of application semantics and behaviors. In this paper, we advocate application-level wear management, which allows us to create effective and flexible wear reduction and leveling techniques for specific application domains. Particularly, we find that applications running with dynamic binary translation (DBT) exhibit significantly more writes. This is because DBT systems need to handle architectural differences when translating instructions across different architectures. In this paper, we present WDBT, which focuses on wear reduction and leveling for DBT systems on NVM. WDBT is designed based on common practices of DBT systems to reduce the majority of writes introduced by DBT. We also implement a prototype of WDBT using a real-world DBT system, QEMU, for multiple popular instruction sets. Experimental results on SPEC CPU 2017 show that WDBT can effectively reduce writes by 52.09% and 34.48% for x86-64 and RISC-V, respectively. Moreover, the performance overhead of WDBT is negligible.

Improving NVM Lifetime Using Task Stack Migration on Low-End MCU-Based Devices

Tiny embedded devices are cost and energy-sensitive, and high-density emerging non-volatile memory (NVM) can help reduce energy consumption at a fraction of the cost. However, high-density NVM has low write endurance compared to volatile memory, so it is vulnerable to write concentration. Most NVM lifetime improvement studies in the existing embedded environment have distributed writes by modifying the mapping relationship between physical and logical addresses. However, applying the existing wear leveling techniques in low-end MCUs such as ARM Cortex M3/M4 that use only physical addresses is hard. Therefore, we wear-level the write-heavy stack area to improve the NVM lifetime in low-end MCUs. However, since the stack of bare metal applications is difficult to move during runtime, we implement the migration function targeting the task stack of FreeRTOS. The task stack moves based on time, and to avoid the pointer validation problem caused by the movement of the task stack, we migrate the stack under safe conditions. In addition, FreeRTOS uses a single heap to preferentially allocate to low free space, which reduces the degree of freedom where the stack moves, reducing the effect of distributing the writes. To alleviate this problem, we add another heap for the stack migration and introduce circular dynamic allocation in the heap. Through our experiments, the proposed method was about 19.6% larger than the ideal case of maximum write, and the computational overhead was about 0.2%.

Study on the file management method of data storage system for airborne radar.

In order to solve the problem that the air-to-ground data transfer rate is much lower than the radar data rate, the onboard system is commonly used for storing the airborne radar data. However, there are two main problems in the data storage using the traditional file management method. The first is that the frequent data updating of the file allocation table (FAT) and the file directory table (FDT) cause a high frequency of address jumps among the discontinuous areas, which leads to a long response time. The second is that the updating frequencies of the FAT, the FDT and the data region are seriously inconsistent, which results in uneven wear of the three areas. To solve these two problems, a file management method, which optimizes the data writing in the three areas of the FAT, the FDT and the data region, is proposed in this study. An actual measurement is carried out on a data storage system of the airborne radar using the proposed file management method. The result shows that the proposed method significantly reduces the updating frequency of FAT and FDT, and achieves the wear levelling of file area and data region.

A Block Classification Method with Monitor and Restriction in NAND Flash memory

In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.

A Relative Reference Responsive LRU based Page Replacement Algorithm for NAND Flash Memory

The acceptance of NAND flash memories in the electronic world, due to its non-volatility, high density, low power consumption, small size and fast access speed is hopeful. Due to the limitations in life span and wear levelling, this memory needs special attention in its management techniques compared to the conventional techniques used in hard disks. In this paper, an efficient page replacement algorithm is proposed for NAND flash based memory systems. The proposed algorithm focuses on decision making policies based on the relative reference ratio of pages in memory. The size adjustable eviction window and the relative reference based shadow list management technique proposed by the algorithm contribute much to the efficiency in page replacement procedure. The simulation tool based experiments conducted shows that the proposed algorithm performs superior to the well-known flash based page replacement algorithms with regard to page hit ratio and memory read/write operations.