Walden FoM Research Articles

An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC

AbstractThis paper proposes an 8-bit synthesizable SAR ADC with inverter-cell-based capacitive digital-to-analog converters (CDACs). An inverter-cell-based capacitor is proposed by connecting the supply and ground ports of the inverter cells together but leaving them floated to suppress the voltage dependence to be suitable for employment in an ADC with moderate resolution. Furthermore, an inverter-cell-based analog switch is proposed to be employed in S/H and CDAC to achieve a fully standard-cell-based design without any custom-designed cells. The prototype is fabricated in a 65 nm standard CMOS process occupying 0.19 mm2. With a Nyquist input, the SFDR and SNDR reach 53.6 dB and 46.2 dB at 2.92 MS/s respectively without calibration. The power consumption is 425 $${\mu }$$ μ W from a 1.2 V supply, which leads to the Walden FoM of 0.86 pJ/conv.-step.

A 62.2dB SNDR Event-Driven Level-Crossing ADC with SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition.

This paper proposed an event-driven clockless level-crossing ADC (LC-ADC) suitable for biomedical applications. Thanks to the LC loop, the sampling rate of the converter automatically adapts to the input activities. Activity-dependent power consumption and data compression can thus be realized, saving system power, especially during time-sparse signal acquisition. Meanwhile, a SAR-assisted loop is exploited to resolve the loop-delay-induced distortion in conventional LC-ADC. Therefore, the resolution and power efficiency of the LC-ADC are improved effectively while maintaining the event-driven feature. Implemented in a 55nm process, the proposed LC-ADC achieves a scalable power consumption and a peak SNDR of 62.2dB for a 20kHz input. It also achieves a Walden FoM of 29.7fJ/conv.-step and a Schreier FoM of 158.6dB, which is best in class, without using off-chip calibration. Sub μW power is realized when the input frequency is below 1.5kHz. The proposed LC-ADC is also verified by simulated electrocardiogram (ECG), neural spike, and electromyogram (EMG) signals. It provides a ~7X data compression for ECG input, providing an attractive solution for time-sparse signal acquisition in biomedical applications.

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW

Compact, high-bandwidth analog-to-digital converters (ADCs) with moderate resolution are a critical building block in high-speed communication links. In this work, a hybrid time and voltage domain ADC is presented that uses a single high-speed voltage-to-time converter (VTC) as a high-bandwidth sampling buffer for a four-way time-interleaved successive approximation (SAR) ADC. Time-domain encoding also enables a low-power 3b SAR assist time-to-digital converter (TDC) to enhance SAR speed with minimal calibration. A 0.0045 mm2 prototype fabricated in 22 nm fin field-effect transistor (FinFET) CMOS provides 13 GHz effective resolution bandwidth (ERBW) and consumes 6.0 mW with a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 38 dB at 3.8 GS/s, for 24.4 fJ/step Walden FoM.

A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC

This paper presents a novel subranging Sigma-Delta ADC using a relaxation Current-Controlled Oscillator (ICO). The instantaneous frequency of the ICO at the sampling instant determines its time resolution and hence its quantization error, while its average frequency determines its power dissipation. Therefore, running the ICO at nominally lower frequency for most of the sampling period while increasing its frequency close to the sampling instant achieves high resolution and low power consumption. This idea is similar to the strategy employed by athletes in a race where they speed-up close to the finish line to gain a clear lead from others. A prototype ADC is designed and fabricated in TSMC 180nm CMOS technology. It achieves an ENOB of 11.9 bits consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{W}$ </tex-math></inline-formula> of power from a 1.8V supply and occupies an active area of 0.06 mm 2, which corresponds to a Schreier FoM of 156.8 dB and a Walden FoM of 625 fJ/conversion cycle.

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

SummaryThis paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM.

A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration

This paper presents a 1.9-ps 8× phase interpolation time-to-digital converter (PI-TDC). This architecture enhances the resolution and conversion speed in cooperation with phase interpolation, high-frequency readout, and reset techniques. The prototype PI-TDC is designed in a 65-nm CMOS process with a 1-V power supply, achieving a 1.9-ps resolution at 2.5-GS/s. The simulated DNL is 0.85-LSB, and INL is 0.64-LSB. This PI-TDC is applied to a high-speed time-based analog-to-digital converter (TB-ADC) with a high-performance voltage-to-time converter (VTC) and the capacitance compensation self-calibration (CCS-CAL). The high-speed TB-ADC achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting a Walden FoM of 52.1-fJ/conv.-step.

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction

This article presents a 60-MS/s 5-MHz BW noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an integrated highly linear input buffer in a 40-nm CMOS process. A dynamic level-shifting (DLS) technique is proposed to adaptively adjust the output common-mode voltage of the integrated input buffer for different operation phases, achieving the optimal linearity while alleviating the voltage breakdown problem at the capacitive digital-to-analog converter (CDAC) top plate. The mismatch-error-shaping (MES) technique is utilized to minimize the CDAC mismatch, which also generates undesired inter-symbol-interference (ISI) errors as a side effect. An ISI-error correction (IEC) technique is proposed to mitigate this problem and further improve the linearity. Both foreground and background calibrations are adopted in the subranging ADC and the NS filter to improve the gain accuracy. This SAR ADC prototype, with an integrated input buffer driving a 4.4-pF CDAC within 2.7 ns, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR)/total harmonic distortion (THD) of 85.4 dB/84.2 dB/97.3 dBc/86.4 dB/−92.9 dBc while consuming 8.06 mW from 2.5- and 1.1-V dual supply voltages. The Walden FoM (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {W}}$ </tex-math></inline-formula> ) and figure-of-merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {S}}$ </tex-math></inline-formula> ) are 60.6 fJ/conv.-step and 172.1 dB, respectively.

A VCO-Based 2nd-Order Δ2–ΔΣ Modulator for Small-Size High Energy-Efficient Current Sensing Front-End

In this letter, a 2nd-order 2 -Σ modulator consisting of a voltage-controlled-oscillator-based quantizer (VCOQ) and a current digital-to-analog converter (DAC) with a pulse width modulator (PWM) is presented for the precise acquisition of a wide range photocurrent in an area-and energy-efficient form factor. The proposed 2-modulation realized by the 2nd-order infinite impulse response (IIR) filter on the feedback significantly attenuates the magnitude of input signals, enhancing the DR and linearity. Moreover, an additional differentiator followed by the VCOQ features the negative feedback loop in the 2nd-order Σ modulator, improving noise shaping with no additional current DAC noise. In addition, a 1-bit PWM current DAC substituting the multi-bit current DAC is devised to mitigate the noise from the current DAC, realizing the high resolution of 1 pA with 500 Hz bandwidth. The prototype chip fabricated in a 110-nm CMOS occupies 0.0308 mm2 and achieves Walden FoM of 4.15 pJ/conv.

A 0.8-μW and 74-dB High-Pass Sigma-Delta Modulator With OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition.

This work presents a third-order high-pass sigma-delta modulator (HPSDM) for biomedical signal acquisition. The operational amplifier (op-amp) sharing and noise-coupling techniques are adopted to reduce the required quantity of op-amps and add a noise-shaping order, which can achieve low power consumption and high resolution. A novel switched-capacitor architecture is proposed to suppress the increasing in-band noise and alleviate the circuit sensitivity to capacitor mismatch in the high-pass integrator. The proposed HPSDM was fabricated in a 0.18-μm standard CMOS process. Measurement results reveal that the proposed HPSDM has a signal-to-noise and distortion ratio (SNDR) of 75.26/74 dB in 200 Hz bandwidth and consumes 1.52/0.8 μW under 1.2/1 V supply voltage, which can achieve a peak Schreier Figure-of-Merit of 156.45/157.98 dB and a peak Walden FoM of 0.802/0.488 pJ/conv.

A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS

A 12-bit 20-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The macrocells for the capacitive digital-to-analog converter, the bootstrapped switch, and the dynamic comparator are presented. The custom standard cells for the dynamic SAR logic are also presented. By using the macrocells and the custom standard ones, the layout of this SAR ADC is completed by using the DPR tools. Several techniques are presented to improve the parasitic capacitances, the current density of the metal interconnections, and the nonideal effects caused by the DPR tools. This SAR ADC is fabricated in 40-nm CMOS technology and its active area is 0.0067 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To compare with the full-custom method, the proposed DPR flow has speeded up by a factor of 288 to complete the interconnection wires. Its power dissipation is 363 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at 20 MS/s and the calculated Walden FoM is 23 fJ/c. step at Nyquist frequency.

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 15.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {W}$ </tex-math></inline-formula> , resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR &amp; VCO ADC

We present an OTA-free 1–1 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage-controlled oscillator (VCO) as the second stage. The key contribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuation due to passive charge sharing in the NS-SAR to linearize the VCO. The MASH architecture suppresses quantization noise and SAR comparator noise at the ADC output, and the high pass shapes VCO thermal noise. In addition, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16 mW while achieving an SNDR/DR of 71.5/75.8 dB over a 1.1-MHz bandwidth and Walden FoM of 23.3 fJ/step, which is the lowest in 65-nm technology.

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration

This paper presents a nonbinary 2b/cycle SAR ADC structure with two assistant loop-unrolled comparators. By using the reset time of 2-bit comparators, the proposed structure achieves extra single bit conversion after normal 2-bit conversions, thus removing one comparison period compared with conventional 2-bit SAR. A nonbinary decision scheme is realized to relax the DAC voltage settling requirement, especially the signal-DAC voltage for loop-unrolled conversion. Besides, a low kick back noise comparator is adopted with time-based offset calibration, which reduces DAC voltage fluctuation and eliminate offset mismatch. Simulation result shows that the ADC achieves 53.35 dB SNDR at Nyquist input frequency after offset calibration, resulting in a Walden FoM of 28.76fJ/conversion-step.

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS

This paper proposes a high-speed 7/8-bit 800-400 MS/s configurable SAR ADC. With simple control switches, the ADC can work under two different modes with configurable resolution and sampling speed. Nonbinary technique with built-in redundancy in capacitive DAC is used for better linearity as well as improving the conversion speed. Other high-speed techniques, such as spilt switching scheme, asynchronous clock, are also utilized to further increase the conversion speed. A design example in 65 nm CMOS is presented. Simulation results show that with 1.2 V supply, the SNDR at Nyquist input are 43.40 dB and 49.57 dB under 7-bit (800 MS/s) mode and 8-bit (400 MS/s) mode, respectively. The power consumptions are 2.17 mW and 1.36 mW for 7-bit and 8-bit modes, respectively. Therefore, the calculated Walden FOM for 7-bit mode is 22.3 fJ/conversion step and 14.2 fJ/conversion step for 8-bit mode.

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

A 0.56-mW 63.6-dB SNDR 250-MS/s Two-Step SAR ADC in 8-nm FinFET

This paper presents a two-step SAR ADC that uses coarse and fine comparators with dedicated SAR logics and asynchronous clock generators for each comparator to increase the energy efficiency by optimizing comparators and reduce output loading of the comparators and asynchronous clock generators. The relative offset of the two comparators is calibrated by redundancy based offset detection and input transistor transconductance controlled offset correction method without compromising the power. A constant impedance skewed inverter saves reference current with low short circuit current without additional CDAC settling time and logic. The ADC is fabricated in an 8 nm FinFET process, and achieves 63.6 dB SNDR at 250 MS/s while consuming 0.56 mW, resulting in Walden FoM of 1.81 fJ/conversion step.

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

This article proposes a fully dynamic, low-power, wideband, time-interleaved (TI), noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feedforward (CIFF) architecture. Both the interleaving operation and the loop filter are implemented by using the fully passive switched-capacitor circuits. The feedforward summation is realized by a multi-path dynamic comparator. The overall noise transfer function (NTF) is highly robust against process, voltage, and temperature (PVT) variations since the NTF is determined by device ratios. This allows the NTF zeros to be close to 1, with a good NS effect. Compared with a recently published TI NS SAR based on the error-feedback (EF) architecture, this work does not need a static amplifier, thus leading to the fully dynamic operation. Meanwhile, it eliminates the dependence of NTF on the PVT-sensitive amplifier gain. Implemented in a 40-nm CMOS process, the prototype ADC achieves an SNDR of 69.1 dB, a bandwidth of 50 MHz, and a power consumption of 8.5 mW under a 1.1-V supply, leading to a Walden FoM of 36.3 fJ/conv.-step.

A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.

A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array

This paper presents an effective method to arrange high linearity and area-efficient digital-to-analog converter (DAC) to enhance the resolution of successive approximation register (SAR) analog-to-digital converter (ADC). The relationship between ENOB and DAC mismatch error is theoretically analyzed, which gives the guidance of optimizing the mismatch error of DAC array. The parasitic effect on the linearity of DAC can be obtained through a normalized parasitic capacitor model, which evaluates the parasitic capacitors caused by the layout and routing of DAC array. A 10-bit 20 MS/s SAR ADC with redundancy is fabricated with 0.18 μm CMOS process. Measurement results show that the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 57.9 dB and 75.9 dB, respectively. The SAR ADC achieves a Walden FoM (FoMW) of 75.1 fJ/conversion step and occupies a small active area of 0.069 mm2 benefited from the compact layout.

A 348-μW 68.8-dB SNDR 20-MS/s Pipelined SAR ADC With a Closed-Loop Two-Stage Dynamic Amplifier

This letter presents a two-stage dynamic amplifier that achieves the high dc gain and PVT robustness of the residue amplifier in a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier operates in a closed-loop configuration and does not require further calibration. The pipelined SAR ADC occupies 0.065 mm2 in a 65-nm CMOS process. It achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 68.8 dB at a sampling rate of 20 MS/s and draws 348 $\mu \text{W}$ from a 1.2-V supply. This corresponds to a Schreier FoM of 173.4 dB and a Walden FoM of 7.7 fJ/conv.-step. Furthermore, it maintains SNDRs over various sampling rates from 1 to 20 MS/s and its power consumption is scaled linearly.