Abstract
This paper presents a two-step SAR ADC that uses coarse and fine comparators with dedicated SAR logics and asynchronous clock generators for each comparator to increase the energy efficiency by optimizing comparators and reduce output loading of the comparators and asynchronous clock generators. The relative offset of the two comparators is calibrated by redundancy based offset detection and input transistor transconductance controlled offset correction method without compromising the power. A constant impedance skewed inverter saves reference current with low short circuit current without additional CDAC settling time and logic. The ADC is fabricated in an 8 nm FinFET process, and achieves 63.6 dB SNDR at 250 MS/s while consuming 0.56 mW, resulting in Walden FoM of 1.81 fJ/conversion step.
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