3.5 A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques

Abstract

The two-step SAR ADC is an energy-efficient architecture for high-resolution applications, which faces headroom challenges from the voltage-domain residue amplification under a low power supply. A TDC-assisted SAR ADC [1] uses a voltage-to-time converter (VTC) and a TDC as the back-end to quantize the residue voltage of the SAR ADC, which is attractive to the low power supply scenarios by moving the voltage domain quantization of a two-step SAR ADC into the time domain. However, the TDC-assisted SAR ADC encounters several design challenges. For example, it is sensitive to PVT variations due to partial time-domain operation, and its conversion speed is limited significantly by the long VTC latency when there is a small residue input voltage. This paper presents both PVT tracking and speed enhancement techniques for a 13b two-step TDC-assisted SAR ADC with 0.6V supply. The VTC and the back-end TDC are designed to have a common operation characteristic; thereby, their variations over PVT are inherently tracked without the need of any extra power or circuit overheads. The prototype ADC achieves less than 0.8dB SNDR drop across – 50°C to 90°C and ±5% power supply variation at 20MS/s. The Walden FoM is 1.4fJ/conversion-step.