Wafer Shape Research Articles

HYPREZ Wafering Solutions: A Novel Approach of SiC Wafering Solution

A novel approach for processing SiC wafers has been developed to grind then polish 150 and 200mm SiC wafers without lapping. The purpose of this work was to optimize the processing of SiC wafers sliced from boules to finished epi-ready wafers by grinding and chemical-mechanical polishing (CMP). Diamond vitrified wheels were used for coarse and fine grinding to correct the irregular shape of SiC wafers before reducing surface roughness by CMP. 4H-SiC wafers were sliced by diamond embedded/slurry wire saw and laser split techniques. Incoming wafer condition was seen to affect coarse grinding wheel performance depending on incoming surface roughness and shape. Wheel characteristics, including abrasive size, abrasive concentration, and bond structure, were adjusted to improve grinding efficiency based on incoming conditions. Coarse grinding wheels were able to reduce wafer total thickness variation to 3-5um and average surface roughness to 20-30nm (Ra). Fine grinding wheels were optimized to reduce total thickness variation (TTV) below 2um and surface roughness to 1-2nm Ra and peak-to-valley height of 20-30nm (Rt). Coarse and fine wafering time was less than 30 minutes total to remove 50 microns on both Si and C-face per wafer. Surface damage from grinding was removed after one hour of polishing each wafer by CMP, achieving surface roughness of 0.4nm Ra and 5-7nm Rt. The benefit of optimizing coarse and fine grinding of 150 and 200mm SiC wafers is demonstrated by producing flat wafers, which reduced overall processing time to prepare an epi-ready condition by CMP.

Flash memory hole etch profile monitoring using x-ray and optical scatterometry

Memory hole (MH) etching may be one of the most critical and challenging processes in three-dimensional flash processing and integration. As the holes get deep, hole critical dimensions (CDs) can vary significantly during the top-down etch processing, the hole shape can deviate from a round hole, and the centerline of the hole can deviate from a vertical line. These and other complex behaviors depend on not only the process conditions (chemistry, plasma power, bias, temperature, etc.) but also the process chamber history [e.g., radio frequency (RF) hours from preventative maintenance] and how the process chambers are conditioned. In addition, the etch behavior depends on the tier thickness (ONON or OPOP), materials, deposition conditions, and overall wafer topography and shapes. The etch behavior is further related to the die positions on the wafer (center or middle versus edge dies) and the position in the memory cell (close to the edge of the cell or near the center of the cell). To monitor and control the etch behavior, many metrology methods have been developed; these include the etch-back top-view scanning electron microscopy (SEM), tilt SEM, transmission electron microscopy (TEM), and high voltage scanning electron microscopy (HVSEM). These methods are time consuming, and some are destructive, but they have been deemed the ground truth for determining variations in MH etch processes. We report a methodology that combines optical scatterometry (SCD) and small-angle x-ray scatterometry measurements to provide reliable CD profile measurements while meeting the fast-turnaround sampling requirements of high-volume manufacturing.

Shape modulation due to sub-surface damage difference on N-type 4H–SiC wafer during lapping and polishing

The technology enhancement of obtaining 4H–SiC wafers with a concave Si face shape has improved the performance of GaN-on-SiC. For manufacturers, the wafer shape has a tremendous impact on the deposited films quality by increasing defects generation or causing undesirable strain. Therefore, it is crucial to control the wafer shape and explore the mechanism. This study recorded the wafer shape evolution by flatness tester during the machining process of lapping, mechanical polishing (MP), and chemical mechanical polishing (CMP). The varying shapes of SiC wafers are due to surface damage and intrinsic stress caused by the early lapping process, but the intrinsic stress is dominant. The measurement results show that double side MP and single side CMP make the wafer more convex and concave. It indicates that the residual surface stress is involved in shape formation. Perfect symmetrical shape between (0001) Si face and (000 1‾) C face suggests that there is indeed bending stress within the wafer. In this study, atomic force microscopy (AFM), high-resolution X-ray diffractometry (HRXRD), and scanning electron microscopy (SEM) was used to investigate the surface damage between SiC polar faces. According to the results, the damage to the Si face is more severe than that to the C face after double-sided mechanical polishing, leading to the wafer becoming more convex.

Evaluation of Compacted Forage Feed on Kupang Cattle Feeding Behavior

Forage compact feed has the ability to cut the adaptation period of grazing cattle when transported, because they are used to consume forage. The effect of the form and type of forage formulation on the feeding behavior of cattle needs to be studied further to determine the preferences of cattle for this compact feed. This study used 36 cattle with 3 replications in each treatment. The 2 factor groups withfactorial design consisting formulation and form of feed was applied in this study. The forms of feed used in this study were wafers, pellets, dried pellets, and cubes. The formulations used in this study were formulation 1 (10% molasses, 30% indigofera leaves, 50% straw, 10% elephant grass); formulation 2 (10% molasses, 30% indigofera leaves, 60% straw); formulation 3 (10% molasses, 20% indigofera leaves, 65% straw, 5% hemp). The parameters observed in this study were eating behavior of cattle which consisted of the frequency and duration of eating, drinking, rumination, and resting. The results showed that there wasan interaction on eating frequency and cattle duration. Formulation 3 on wafer treatment had the highest feeding frequency (P<0.05). Formulation 1 on wafer treatment had the highest duration of rumination (P<0.05). In the conclusion, Formulation 1 and 3 with wafer shape showed the best behavior for eating.

Effect of grinding residual height on the surface shape of ground wafer

In ultra-precision grinding of the wafer, most existing studies on wafer shape control only consider the kinematic relationship between grinding wheel and wafer, but the influence of grinding residual height on wafer grinding shape cannot be ignored. In this paper, the formula for the distance between the grinding marks formed by adjacent grains was established. Afterward the model of residual height and the model of wafer shape considering the influence of residual height were established. Methods to enhance the flatness of the ground wafer were put forward by changing the process parameters, and changing the inclination angles of the grinding wheel shaft. The residual height under different parameters and the inclination angles needed to offset the influence of residual height on the wafer shape were simulated and analyzed. Finally, the trial experiments were conducted to verify the proposed methods and the wafer shape model. The study outcomes will provide helpful instruction for ameliorating the flatness of the wafer.

Technique for investigation of the shape changes of wafers and thin-film membranes by using geomorphometric approaches

We discuss a technique for investigating changes in complex topography and shape of structures using geomorphometric methods to study surfaces of wafers and membranes formed by the Bosch process. The wafers were analyzed before and after the deposition of the SiO2 layer. The membranes were analyzed during the bulge testing. The study was carried out using maps of the catchment area and principal curvatures taking into account artifacts of the approximation of experimental data. We found a correspondence between the distribution of lines connecting the highest surface areas before and after the deposition of the SiO2 layer on the wafers. For membranes with structure: Al(0.8 μm)/SiO2(0.6 μm)/Al(1.1 μm), pSi*(0.8 μm)/SiNx(0.13 μm)/SiO2, Al(0.6 μm) we also found that features of membrane boundaries are mainly caused by their initial shape rather than change under the action of an applied pressure. The advantages of geomorphometric methods for studying changes in the shape of wafers and thin-film membranes in technological processes for the manufacturing of microelectronic devices are shown in comparison with traditional methods for analyzing surface topography maps. Keywords: thin films, membrane, defect, mechanical characteristics, mechanical stresses, deformation, deflection, strain, microelectromechanical systems, MEMS, circular membrane, silicon substrate, optical profilometry, overpressure, geomorphometry, Gaussian curvature, warpage, principal curvatures, wafer, bulge testing, bulging method, thin-layer coating, digital elevation models, DEM, surface, topography.

Методика исследования изменения формы пластин и тонкопленочных мембран с использованием геоморфометрических подходов

We discuss a technique for investigating changes in complex topography and shape of structures using geomorphometric methods to study surfaces of wafers and membranes formed by the Bosch process. The wafers were analyzed before and after the deposition of the SiO2 layer. The membranes were analyzed during the bulge testing. The study was carried out using maps of the catchment area and principal curvatures taking into account artifacts of the approximation of experimental data. We found a correspondence between the distribution of lines connecting the highest surface areas before and after the deposition of the SiO2 layer on the wafers. For membranes with structure: Al (0.8 μm)/SiO2 (0.6 μm)/Al (1.1 μm), pSi*(0.8 μm)/SiNx (0.13 μm)/SiO2, Al (0.6 μm) – we also found that features of membrane boundaries are mainly caused by their initial shape rather than change under the action of an applied pressure. The advantages of geomorphometry methods for studying changes in the shape of wafers and thin-film membranes in technological processes for the manufacturing of microelectronic devices are shown in comparison with traditional methods for analyzing surface topography maps.

Non-contact grinding/thinning of silicon carbide wafer by pure EDM using a rotary cup wheel electrode

The significantly increased stability of third-generation semiconductors, both mechanically and chemically, presents a significant challenge to traditional wafer grinding. This study develops pure electrical discharge machining as an alternative for non-contact wafer grinding and thinning to achieve high precision and low cost. This method employs a copper-made rotary cup wheel as the tool electrode to replace the conventional diamond wheel to realize electrical discharge grinding. A prototype is built to evaluate the new process with single-crystal SiC. Aiming at ultra-precision machining, the material response of SiC to both single and consecutive discharge is elucidated. The influencing mechanism of pulse conditions on hard, brittle crystalline SiC material is demonstrated via experiments and simulation. Further, the material removal behavior, grinding stability, surface integrity, wafer shape accuracy, and process-induced subsurface damage are comprehensively investigated via single and consecutive discharge experiments under various conditions. In addition, the extreme precision that is achievable by contemporary EDM technology is explored. As a result, a 30 μm thin Φ20 mm SiC wafer with a subsurface damaged layer <1 μm was obtained, showing the potential of EDM for the processing of third-generation semiconductor wafers.

Kinematic Prediction and Experimental Demonstration of Conditioning Process for Controlling the Profile Shape of a Chemical Mechanical Polishing Pad

The uniformity of the wafer in a chemical mechanical polishing (CMP) process is vital to the ultra-fine and high integration of semiconductor structures. In particular, the uniformity of the polishing pad corresponding to the tool directly affects the polishing uniformity and wafer shape. In this study, the profile shape of a CMP pad was predicted through a kinematic simulation based on the trajectory density of the diamond abrasives of the diamond conditioner disc. The kinematic prediction was found to be in good agreement with the experimentally measured pad profile shape. Based on this, the shape error of the pad could be maintained within 10 μm even after performing the pad conditioning process for more than 2 h, through the overhang of the conditioner.

Influence Function Measurement Technique Using the Direct and Indirect Piezoelectric Effect for Surface Shape Control in Adaptive Systems

Since the introduction of adaptive systems for corrective measures, static and dynamic disturbances have been reduced through the manipulation of surface shape in a well-controlled manner. One important application where adaptive systems are highly needed is in the future photo-lithography machines, particularly the wafer table where disturbances affect overlay and focus performance. To reduce overlay and focus errors, a dense array of actuators must be integrated into the wafer table to apply both in- and out-of-plane corrective deformations to the wafer surface. To realize a certain wafer shape, influence functions are linearly superimposed. Accurate models of the influence functions result in an accurate prediction of the final wafer shape. To reduce calibration errors, the influence function of every actuator needs to be determined. Here, we propose a technique to rapidly measure the influence function: the influence function measurement (IFM) technique. Using the actuate-sense property of piezoelectric materials, the influence function is determined by activating one piezo-actuator and measuring the charge induced on the neighboring piezo-actuators. The measured charges are compared to the results of finite element simulations and the absolute difference of 0.3 &#x0025; is reported for the inter-actuator charge coupling parameters. This clearly indicates the potential of the proposed technique. <i>Note to Practitioners</i>&#x2014;A critical step during the integrated-circuit lithographic fabrication process is the exposure. A particular practical challenge in this step is to correct for the mismatch between the optical image plane and the wafer surface, caused by wafer deformations. The mismatch negatively impacts the overlay and focus performance. To reduce the mismatch, actuators can be embedded into the wafer table to counteract wafer deformations, where the overall wafer surface shape is a superposition of each actuator&#x2019;s influence function. As part of the calibration for the embedded actuators, their influence functions are measured and stored. However, errors arise when influence functions are not measured for every actuator. Additionally, for different wafers, the influence functions vary hence the calibration should be done per wafer. This calibration process takes time and should not influence throughput. Our paper presents a viable approach that reduces the calibration time of active wafer tables, which is also relevant for other adaptive systems such as deformable mirrors. Since the technique requires the actuators to be mechanically coupled, it is limited to continuous surfaces. The proposed technique is numerically tested and experimentally verified to demonstrate performance.

(Invited) P-Type and N-Type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

Silicon Carbide is rapidly growing in the power electronics industry. It is fueled by several robust long-term growth markets like renewables, cloud computing and electric vehicles. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. There is a continuous push in subsequent generations to improve device performance, reliability and efficiency. Some of the advanced design concepts in Silicon like super-junction technology have significant manufacturing roadblocks like diffusion, epi regrowth and implantation. In this work, we present results of both p-type and n-type channeled implants into 4º offcut N-type SiC substrates and Epitaxial layers using a Nissin Ion Equipment IMPHEAT system. Deep-channeled implants can be considered an enabling technology for the fabrication of advanced device designs including super-junction structures.The use of channeled implants have been reported on on-axis [1] SiC and 4º offcut using primarily low energies [2,3]. One major concern while trying to check the feasibility of channeling and implement it in mass-production is the reliability and variation of the off-cut angle. Fig. 1 shows the off-cut angle reported by the substrate vendor and the actual offcut angle as measured by X-ray diffraction. The actual off-cut variation is comparatively low. However, per wafer inline XRD measurements might be needed for accurate channeling. Fig. 2 shows how a 960kev 1e13cm-2 dose channeled implant changes the wafer shape. This change in shape is consistent with other high temperature treatments like Epi growth. Fig. 3 shows the room temperature channeled and non-channeled implant of triple charged Aluminum at 960 keV with a dose of 1e13cm-2. The offcut angle as measured by XRD of 4.1º gives the maximum range. The implant is also not very sensitive to off-cut disorientation. Fig. 4 shows the channeled implants as a function of implantation temperature. As expected, the range is reduced and thereby restricts very high doses. Fig. 5 shows similar channeled and non-channeled implantation of Boron and Phosphorous. The phosphorous profiles are flat and can be effectively used for n-type doping. A comprehensive review of effects of dose and orientation on the channeled profiles will be presented. Channeled implanted wafers were activated and the activation measured by fabricating Metal Schottky contacts. The effect of high and low warp wafers on channeled implant profiles are also discussed. Further implants at different energies are obtained and combined to get box-like profiles. The error in off-cut degree that can be tolerated for channeled implants in mass-production is estimated for different energies. Implications to super-junction device fabrication is discussed.

Investigation of Post-Bond Distortion in Direct Wafer Bonding

As device sizes continue to shrink, accurate alignment in semiconductor wafer bonding process becomes more important. In the case of two patterned wafers directly bonded together, proper alignment of the electrical connections between the two bonding surfaces is critical. Misalignment between the wafers during bonding may lead to degraded electrical performance or even device failure. In the case of a patterned wafer directly bonded onto a blank carrier wafer, the relative displacement along the bonded interface is important for subsequent steps. This relative displacement contributes to overlay error in lithography steps. Furthermore, as device density continues to increase, pre-bond wafer shapes become more complex while warp magnitude increases. The distortion contribution from pre-bond wafer shapes becomes more significant as a result. Therefore, it is important to understand the direct wafer bonding distortion mechanics to reduce the yield impact of the process.This paper develops a mechanics model to study wafer bonder performance. An axisymmetric solid mechanics model simulates the wafer bonding dynamics by using a rate-dependent adhesion model. This simulation model includes calibration parameters to tune against experimental results. Using the optimized calibration parameters, an extended 3D simulation model studies more complex phenomena. This paper will report the simulation results that include local variations in wafer properties, clamping and thermal fluctuation effects. Distortion impact due to pre-bond wafer shapes, such as the relative contributions from the pre-bond wafer pair, is also discussed.The results of this model can enable improved hardware optimization to address stricter distortion requirements. This model can optimize key hardware features in lieu of large number of wafer tests to minimize the cost of development. Using this model, target performance can be achieved with fewer hardware iterations and reduce development time. Bonder recipes can also be designed and optimized to account for pre-bond wafer characteristics.

Investigation of Post-Bond Distortion in Direct Wafer Bonding

Direct wafer bonding process is used in semiconductor manufacturing for heterogeneous integration of devices. When two silicon wafers are directly bonded together, the alignment along the bonded interface is critical to device performance and yield. This paper studies the relative alignment, or post-bond distortion, of a direct wafer bonding process using finite element simulation method. The methodology of constructing a 2D axisymmetric model to calibrate a 3D model is discussed. The simulation results showed that the post-bond distortion was sensitive to upper wafer pre-bond shapes and does not depend on lower wafer shapes. The simulation models enable reduced hardware development costs and time.

Progress in Bulk 4H SiC Crystal Growth for 150 mm Wafer Production

The thermoelastic stress, mechanical properties and defect content of bulk 4H n-type SiC crystals were investigated following adjustments to the PVT growth cell configuration that led to a 40% increase in growth rate. The resulting 150 mm wafers were compared with wafers produced from a control process in terms of wafer bow and warp, and dislocation density. Wafer shape was found to be comparable among the processes, indicating minimal impact on internal stress. Threading edge and threading screw dislocation densities increased and decreased, respectively, while basal plane dislocation densities were unaffected by the increase in growth rate. Loss of wafer planar stability was observed in certain cases. The elastic modulus was measured to be in the range of approximately 420-450 GPa for selected stable and unstable wafers, and was found to correspond to resistivity.

Evolution of lattice distortions in 4H-SiC wafers with varying doping

Lattice distortions (LD) in 4H-silicon carbide (SiC) wafers were quantified using synchrotron X-ray rocking curve mapping (RCM), and were resolved into their two components of lattice strain (Δd/d) and lattice plane curvature (LPC) for 150 mm diameter wafers. The evolution of these LDs were investigated for three sequential substrates from the same boule, one of which was the substrate reference, and the other two had a 10 µm thick, 1 × 1017 and 4 × 1014 cm-3 n-type doped epitaxial layer. The lattice strain, Δd/d, was highest for the lowest doped wafer due to higher mismatch with the substrate wafer. After epitaxial layer growth, the LPC variation across the wafer increases by a factor of 2, irrespective of doping. The LPC maps indicate presence of a twist in the lattice planes that increases after epitaxial growth. The LPC component has higher influence on wafer shape change, which can reduce device yields. The lattice strain component predominantly affects the glide of basal plane dislocations (BPDs), thereby reducing device reliability. From analysis of peak widths, it was determined that threading dislocations in the top 6 microns of the wafer increase after epitaxial layer growth.

Impact of Subsurface Damage on SiC Wafer Shape

The impact of surface stress due to polish and grind processes on wafer bow was studied as a function of abrasive size. Results indicate that sub-surface damage from these processes can introduce significant surface stress. For polishing processes, this stress is proportional to mean abrasive size. The study also investigates stress as a function of depth below the wafer surface and finds that most stress is concentrated near the wafer surface.

Effect of Quartz Crystal Form on the Measurement Performance of Multi-dimensional Force Sensor

Quartz wafer is an important part of the force sensor of piezoelectric multi-dimensional force sensor. Its structural form affects the overall measurement performance of force-sensitive components and sensors. In this paper, the shape of the quartz crystal group was first analysed, and then two different types of quartz crystal group models were established using finite element software, and their simulation analysis was performed. The corresponding relationship between the deformation of the two different shapes of quartz crystal set under the same external load and the limitation of external space size was studied. The same axial load and tangential load were applied to two different types of quartz crystals respectively, and the corresponding maximum equivalent stress and stress distribution regions were obtained. This paper provides an important reference for the fabrication of quartz crystal arrays and the selection of quartz wafer shape for piezoelectric multi-dimensional force sensors.

Optimization of 150 mm 4H SiC Substrate Crystal Quality

Continuous optimization of bulk 4H SiC PVT crystal growth processes has yielded an improvement in 150 mm wafer shape, as well as a marked reduction in stacking fault density. Mean wafer bow and warp decreased by 26% and 14%, respectively, while stacking faults were nearly eliminated from wafers produced using the refined process. These quality enhancements corresponded to an adjustment to key thermal parameters predicted to control intrinsic crystal stresses, and a reduction in crystal dome curvature.

Advanced in-situ control for III-nitride RF power device epitaxy

In this contribution, the latest improvements regarding wafer temperature measurement on 4H-SiC substrates and, based on this, of film thickness and composition control of GaN and AlGaN layers in power electronic device structures are presented. Simultaneous pyrometry at different wavelengths (950 nm and 405 nm) reveal the advantages and limits of the different temperature measurement approaches. Near-UV pyrometry gives a very stable wafer temperature signal without oscillations during GaN growth since the semi-insulating 4H-SiC substrate material becomes opaque at temperatures above 550 °C at the wavelength of 405 nm. A flat wafer temperature profile across the 100 mm substrate diameter is demonstrated despite a convex wafer shape at AlGaN growth conditions. Based on the precise assignment of wafer temperature during MOVPE we were able to improve the accuracy of the high-temperature n-k database for the materials involved. Consequently, the measurement accuracy of all film thicknesses grown under fixed temperature conditions improved. Comparison of in situ and ex situ determined layer thicknessess indicate an unintended etching of the topmost layer during cool-down. The details and limitations of real-time composition analysis for lower Al-content AlGaN barrier layers during transistor device epitaxy are shown.

A new method for measuring the flatness of large and thin silicon substrates using a liquid immersion technique

Flatness measurements of thin and large substrates are greatly affected by gravity. In this work, a new method was proposed for accurately measuring the flatness error of large and thin silicon wafers using a floating technique. In this method, a silicon wafer was immersed in a liquid that had a density slightly lower than that of silicon and was supported by three ball supporters in the liquid. The wafer shape was measured using a laser triangulation sensor. The buoyancy force on the wafer inside the liquid could cancel out most of the effect of gravity. The residual effect of gravity was further removed by subtracting the residual deflection calculated by finite-element modeling from the measured result. The method was validated by comparing the flatness values of a thick wafer measured using this method and via a commercially available interferometer. The deformations of wafers ground by #600 and #2000 diamond wheels were measured and the measurement error was less than 3% of the total deformation.