Investigation of Post-Bond Distortion in Direct Wafer Bonding

Abstract

As device sizes continue to shrink, accurate alignment in semiconductor wafer bonding process becomes more important. In the case of two patterned wafers directly bonded together, proper alignment of the electrical connections between the two bonding surfaces is critical. Misalignment between the wafers during bonding may lead to degraded electrical performance or even device failure. In the case of a patterned wafer directly bonded onto a blank carrier wafer, the relative displacement along the bonded interface is important for subsequent steps. This relative displacement contributes to overlay error in lithography steps. Furthermore, as device density continues to increase, pre-bond wafer shapes become more complex while warp magnitude increases. The distortion contribution from pre-bond wafer shapes becomes more significant as a result. Therefore, it is important to understand the direct wafer bonding distortion mechanics to reduce the yield impact of the process.This paper develops a mechanics model to study wafer bonder performance. An axisymmetric solid mechanics model simulates the wafer bonding dynamics by using a rate-dependent adhesion model. This simulation model includes calibration parameters to tune against experimental results. Using the optimized calibration parameters, an extended 3D simulation model studies more complex phenomena. This paper will report the simulation results that include local variations in wafer properties, clamping and thermal fluctuation effects. Distortion impact due to pre-bond wafer shapes, such as the relative contributions from the pre-bond wafer pair, is also discussed.The results of this model can enable improved hardware optimization to address stricter distortion requirements. This model can optimize key hardware features in lieu of large number of wafer tests to minimize the cost of development. Using this model, target performance can be achieved with fewer hardware iterations and reduce development time. Bonder recipes can also be designed and optimized to account for pre-bond wafer characteristics.