Wafer Scale Integration Research Articles

Porous Silicon-Based Optoelectronic Devices: Processing and Characterization

ABSTRACTA patterning process compatible with conventional Si electronics technology, which has resolution better than 5 μm, has been developed in order to perform selected-area anodic etching for producing luminescent porous Si layers (PSL). Correlations between the anodic etching and photolithographic parameters have been identified, and their effects on the resolution and luminescence of porous Si layers have been studied. Finally, the first monolithic processing, i.e., true wafer-scale integration, of a Si-based visible light-emitting diode (LED) and a photodetector using conventional Si technology has been demonstrated.

Fabrication Process of Porous Silicon-Based Optoelectronic Devices

ABSTRACTA patterning process compatible with conventional Si electronics technology, which has resolution better than 5 μm, has been developed in order to perform selected-area anodic etching for producing luminescent porous Si layers (PSL). Correlations between the anodic etching and photolithographic parameters have been identified, and their effects on the resolution and luminescence of porous Si layers have been studied. Finally, the first monolithic processing, i.e.,. true wafer-scale integration, of a Si-based visible light-emitting diode (LED) and a photodetector using conventional Si technology has been demonstrated.

Erratum to: Wafer Scale Integration: A university perspective

Erratum to: Wafer Scale Integration: A university perspective

An intelligent sensor integrated preprocessing facility for neural networks

An innovative concept for parallel image sensing and preprocessing as an interface to artificial neural networks is presented: The architecture is based on a parallel preprocessor system, integrated sensor elements, and readout electronics on a single chip using CMOS wafer scale integration. The components of the system are shortly described. The application of the system is illustrated by the example of an image preprocessing algorithm.

Silicon vertex detector design for B-physics at the FNAL and SSC colliders

Abstract Silicon vertex detectors will be crucial to the success of high rate bottom physics experiments at hadron colliders. A geometrical layout and detector segmentation scheme is presented that is optimized for the production and decay properties of b-particles. While existing p - i - n diode sensors are adequate, new VLSI readout electronics must be developed that are faster and more radiation tolerant than existing devices. Technology is available from the telecommunications industry for streaming the data off the vertex detector. This information can be manipulated with wafer-scale integration processors for use in triggering.

On synthesizing optimal family of linear systolic arrays for matrix multiplication

The authors describe a family of linear systolic arrays for matrix multiplication exhibiting a tradeoff between local storage and the number of processing elements (PEs). The design consists of processors hooked into a linear array with each processor having storage s, 1<or=s<or=n, for n*n matrix multiplication, where the number of processors equals n times the least integer >or=n/s. The input matrices are fed as two speed data streams using fast and slow channels to satisfy the dependencies in the usual matrix multiplication algorithm. While a family of linear arrays have been synthesized for this problem, this technique leads to simpler designs with fewer number of processors and improved delay from input to output. All these designs use the optimal number of processors for local storage in the range 1<or=s<or=n. The data flow is unidirectional, which makes the designs implementable on fault wafer scale integration models.<<ETX>>

WASP: A WSI Associative String Processor

ASP (Associative String Processor) modules (and support software) comprise highly-versatile and fault-tolerant building-blocks for the simple construction of dynamically-reconfigurable low-MIMD/high-SIMD second-generation Massively Parallel Processor (MPP) systems. Indeed, based on state-of-the-art microelectronics and packaging technologies, ASP modules constitute a family of packaged MPP configurations for the cost-effective implementation of highly-compact application-specific high performance information processing systems. Based on scalar-vector content-matching rather than location addressing, ASP substrings comprise homogeneous fine-grain SIMD MPP structures, which, in operation, execute a form of set processing (i.e. a sequence of scalar-vector and vector-vector processes) on relevant data. Moreover, application flexibility enables simple tailoring of parallel processing power to match user requirements. WASP devices are WSI (Wafer Scale Integration) implementations of ASP substrings and, as such, constitute fundamental building blocks for the assembly of ASP modules. Exploiting either monolithic or hybrid 1 μm CMOS WSI technologies, 8,192-processor WASP devices would enable the assembly of 65,536-processor SEM-E compatible ASP modules achieving 10 Tera-OPS/ft3, 1 Giga-OPS/W and 1 Mega-OPS/$ in cost-effectiveness. The paper discusses second-generation MPP design targets and describes ASP modules for real-time signal and data processing applications. In particular, the paper focuses on the architecture, operation, and implementation of the WASP device and reports on the progress of its development.

Wafer Scale Integration: A university perspective

This paper presents the Wafer Scale Integration research underway at our university. Specifically, we focus here on theApplications, Architectures, Design, and Test areas. Discussed are the philosophy of such an--admittedly aggressive--effort, the evolving infrastructure for the project, the application-driven architectures developed, and the design and test methodology. The first WSI design is a fully parallel FFT wafer, with application to a high-performance, high-speed CW jamming canceller. Other wafer level designs include an L-U decomposition array, using a newly-developed reciprocal cell, and a multipurpose PE array. The transition from basic tools, such as MAGIC, to commercial tools such as CADENCE, and the importance of a high level description language, VHDL, for modeling and simulation is emphasized. The discipline of reconfiguration, and the associated yield models, incorporating a harvesting factor, are also an integral part of the on-going project. Although, the first wafer will be reconfigured usingLaser linking and Cutting on the in-house laser table, alternative recon-figuration approaches for the other wafer designs are also being considered.

A fault-tolerant array processor designed for testability and self-reconfiguration

The design of a fault-tolerant rectangular array of processing elements (PEs) is presented in which the reconfiguration is done by means of on-chip distributed logic, without the help of any external host. Spare PEs are included in every column of the array, and faulty PEs are bypassed within a column to facilitate reconfiguration in the presence of faults. Scan paths are used to enhance the testability of the array. PEs are tested locally using near-neighbor comparisons without the need of an external host. Because the interconnections between logical neighbors are short, the speed penalty for reconfiguration is very small. Any amount of redundancy can be incorporated in the array without changing the topology of the scheme or the design of the reconfiguration switches. The scheme is well suited for very large-area, high-density chips and wafer-scale integration. In order to demonstrate the capabilities of the scheme and evaluate its performance, an experimental chip consisting of a 6*4 array was designed, fabricated, and tested. Details of the design and the implementation of the chip are presented. The scheme is also analyzed for yield and area utilization for a range of array sizes and PE survival probabilities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Ultra large scale static rams

Using a patented defect avoidance technique, high yield production of high density SRAM devices (ULSI SRAMs) can be achieved one process generation ahead of the rest of the industry. Production wafer yields as high as 100% and long-term average yields above 80% are reported on Inova's monolithic, 1.2μ, 320 square mm, one megabit SRAM demonstrating a practical method of achieving wafer scale integration. A yield model is presented and used to determine the optimized architecture and redundancy scheme for Inova's four megabit SRAM and to predict yield as a function of defect density. Achievement of a working 8M-bit experimental device using a 1.2μ process is also reported.

Petri net performance modeling of a modified mesh-connected parallel computer

A new message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is designed to be a general-purpose parallel architecture suitable for wafer scale integration. Stochastic Petri nets (SPN) are used to model the behavior of the MMCPC. Both the one-dimensional and two-dimensional SPN models of the MMCPC are presented.

The drive to the year 2000

The pace of advances in semiconductor technology over the last four decades is examined, and projections are made for the decade ahead. Predictions are made in the areas of memory, logic chips, wafer-scale integration, digital signal processing, communication chips, and neural networks, and problems are identified. Also discussed are GaAs, superconducting devices, optical computing, molecular computing, mass storage technologies, and handwriting and speech recognition. It is noted that maintaining the pace of technology development during the next ten years will take huge investments and that such funds must ultimately come from the marketplace. It is concluded that the major challenge is to expand the microcomputer market through new applications and more intensive consumer use of existing products. >

PEST: A Tool for Implementing Pseudo-Exhaustive Self-Test

Multichip modules, wafer-scale integration, and three-dimensional connections are the latest solutions to building faster computers. These new technologies will shorten electron travel distance, but they will compound an existing problem: testing. Without a systematic approach, testing even a single very large-scale integrated (VLSI) chip could be impossible. This paper describes a superior built-in self-test (BIST) design methodology that solves the VLSI testing problem. Pseudo-exhaustive self-test (PEST) is a design methodology that provides effective, 100-percent fault coverage without the need for fault simulation or deterministic test generation. We used PEST, an existing software package based on the algorithms discussed here, to implement the PEST function in three VLSI designs at AT&T.

Manufactures consider fixtureless in-circuit testers : M. Takahishi. JEE (Japan) 58 (November 1990)

This chapter discusses the packaging-related reliability issues. Packaging technology is changing rapidly to keep up with the demands of continuously increasing levels of circuit integration. Beginning with ceramic dual in-line packages (DIPs), the trends shifted to plastic packages and at present there is an increasing emphasis on leadless chip carriers (LCCs) in both ceramics and plastics. The LCCs have influenced the printed circuit board (PCB) assembly technology as well. The DIPs require through-hole mounting of components, whereas the LCCs are mounted on the surface of the PCB. This change has led to the development of surface mount technology (SMT) for surface-mounted components (SMCs) or devices (SMDs). The SMDs require special J-leads. Flip-chip technology is characterized as quick, easy, and reliable and is suitable for multichip hybrids involving thousands of interconnections. Each of these packaging technologies has some unique reliability problems. The wafer-scale integration (WSI) is a manufacturing concept that has been considered from time to time for creating extremely dense packaging of integrated circuits.

A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems

AbstractA method of fabrication defect recovery in ULSI (ultra‐large scale integration) and WSI (wafer‐scale integration) arithmetic operation systems involving fault tolerance based on residue arithmetic is presented. The implementation of the fault‐tolerant system, which includes a compact multiplexed error correcting circuit, is described. Analysis of the yield of redundant systems based on the proposed method indicates that the effect chip area of redundant ULSI/WSI systems can be extended to 10 to 20 times that of a nonredundant VLSI chip while maintaining a yield of 50 percent.

Defect cluster analysis for wafer-scale integration : Paul R. Pukite and Claude L. Berman. IEEE Trans. Semicond. Mfg3(3), 128 (1990)

Defect cluster analysis for wafer-scale integration : Paul R. Pukite and Claude L. Berman. IEEE Trans. Semicond. Mfg3(3), 128 (1990)

A Proposed Design Approach for a Martian Spaceship Electronic Brain

Recently announced idea of a multinational manned Martian expedition should be reliably based on high-level autonomy. The basic element of autonomy is an onboard fault-tolerant computer system (FTCS). This paper discusses a new highly efficient dense packaging concept for a FTCS which emphasizes avionics maintainability and allows the crew to repair this most critical spaceship system during deep space mission without soldering or welding operations. The architecture developed within the research is called the Wafer-Scale Integration Dice Element System (W-SIDE System). It is oriented for easy-to-repair applications and can be tailored to achieve the specified reliability. Martian spaceship electronic brain is an example of a possible artificial intelligence implementation of a so-called dice concept described here.

Multilayer ceramic packaging alternatives

The state of the art in multilayer substrates for integrated circuit (IC) packaging is reviewed. The characteristics, advantages, and disadvantages of the following materials systems are presented: alpha Al/sub 2/O/sub 3/, BeO, AlN, SiC, Si/sub 3/N/sub 4/, BN, mullite, cordierite, glass-ceramics, low-K composites, and polymer systems such as polyimide. These are discussed in single dielectric configurations and more complex systems such as the thin-film multichip module (TFMCM), Si-on-Si wafer-scale integration (SOSWSI), and packaging schemes that incorporate passive components such as capacitors in the substrate. The following conclusions are drawn: (1) the package is less and less just a protective environment and more and more a key functional part of the entire electronic system; (2) the systems manufacturer will play an increasingly important role as the creator of the package; (3) the multichip module (MCM) will slowly be replaced by such schemes as SOSWSI and especially TFMCM; and (4) while Al/sub 2/O/sub 3/ will continue to dominate the materials field, a number of other materials will be increasingly used, especially AlN and SiC, wherethermal dissipation is key, and Cu/polymer systems, where low dielectric constants are required.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Generalized planar matching

In this paper, we prove that maximum planar H-matching (the problem of determining the maximum number of node-disjoint copies of the fixed graph H contained in a variable planar graph G) is NP-complete for any connected planar graph H with three or more nodes. We also show that perfect planar H-matching is NP-complete for any connected outerplanar graph H with three or more nodes. The results generalize and unify several special-case results proved in the literature. The techniques can also be applied to determine the complexity of several problems, including the optimal tile salvage problem from wafer-scale integration and the classic dots and boxes game. Although we prove that the optimal tile salvage problem and others like it are NP-complete, we also describe provably good approximation algorithms that are suitable for practical applications.

A Systolic Array Solution for the Assignment Problem

A systolic array for the solution of the assignment problem is presented. The algorithm requires O(n2) time and an orthogonally connected array of (n+2)*(n+2) cells consisting of simple adders and control logic. The design is area-efficient and incorporates the new concept of a Systolic Control Ring (SCR) to generate the necessary systolic wavefronts in any orientation within the design, while special cells are positioned only on the periphery of the design. The resulting Assignment Problem Iteration (API) is suitable for Wafer Scale integration using only single input and output for data permitting low bandwidth.