Wafer Processing Research Articles

Study on Warpage and Reliability of Fan-Out Interposer Technology

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI.

400 Gb/s O-band silicon photonic transmitter for intra-datacenter optical interconnects.

We present and experimentally demonstrate a silicon photonic (SiP)-based four-lane 400 Gb/s transmitter for fiber-rich intra-datacenter optical interconnects. Four parallel SiP series push-pull traveling wave Mach-Zehnder modulators (MZMs) operating in the O-band are used in the transmitter. The MZMs have an average electro-optic (EO) bandwidth of approximately 30 GHz at 3 V reverse bias voltage. To assess the parallel operation, we measure the EO crosstalk between the four MZMs, where the EO crosstalk between the closest MZMs is below -17 dB over 50 GHz bandwidth. Then, we use a four-channel digital-to-analog converter (DAC) to simultaneously drive the MZMs and characterize the performance of the transmitter versus various parameters. Results reveal that 53 Gbaud pulse amplitude modulation over 4-levels (PAM4), i.e., 100 Gb/s net rate, per lane can be received at a bit error rate (BER) below the KP4- forward error correction (KP4-FEC) threshold of 2.4×10-4 using only a 5-tap feed-forward equalizer (FFE) at the receiver. In addition, we show that 53 Gbaud and 64 Gbaud PAM4 per lane can be received at a BER below the KP4-FEC and 7% hard decision FEC (HD-FEC), respectively, using a driving voltage swing below 1.8 Vpp. To the best of our knowledge, these are the best results for 100 Gb/s PAM4 using a single electrode SiP TWMZM with a lateral PN junction in a multi-project wafer process. Finally, we show that the BER is still below the KP4-FEC at maximum crosstalk for all lanes, and an aggregate rate of 400 Gb/s can be achieved at an average BER of approximately 1×10-4.

PENERAPAN HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) PADA PROSES PRODUKSI WAFER ROLL [Implementation of Hazard Analysis and Critical Control Point (HACCP) in Production of Wafer Roll

The purpose of this study was to determine the application of Hazard Analysis and Critical Control Points (HACCP) to identify and prevent potential hazards in the production process of chocolate roll wafers at PT. X. The production process of wafer roll at PT. X consisted of mixing raw materials, filtering, roasting, rolling a wafer roll, filling cream, cutting, decreasing wafer roll temperature, packaging, and X-ray detection. The implementation of a quality assurance system must be carried out at every stage of processes to prevent microbiological chemical, and physical hazard pollution, and maintaining product quality. The study was conducted using a survey method, by directly following the entire process of making chocolate roll wafers from the receiving of raw materials to the final product in the packaging. The data was analyzed using descriptive analysis method. The application of the HACCP system at PT. X through two steps, that were preliminary hazard analysis step and hazard analysis step. The results showed that the X-ray detection pathway found CCP contamination of foreign objects with significant hazards in the form of metal parts in the product. Preventive actions taken included separating and marking deviant products, repairing the auto stop system, and visual observation by employees on X-ray detection machines.

Pyramid size control and morphology treatment for high-efficiency silicon heterojunction solar cells

This paper investigates the formation process of surface pyramid and etching characteristics during the texturing process of mono-crystalline silicon wafers. It is found that there is an etch rate transition point in alkaline anisotropic etching when {100} plane-dominated etch turns to {111} plane-dominated etch, and the pyramid size has a strong linear correlation with the etch amount at the transition point. Several techniques were developed to control the pyramid size by monitoring and adjusting the etching amount. A wide range of average pyramid sizes were successfully achieved, from 0.5 to 12 μm. The experiments of the pyramid size on the light reflectance, the minority carrier lifetime (MCLT), and the performance of silicon heterojunction (SHJ) solar cells were carried out and analyzed. A desirable range of pyramid sizes was empirically determined by our investigation. In order to reduce the density states on the texturing surface, the wet-chemical smoothing treatment was also investigated. The smoothing treatment improves the passivation quality and the performance of the solar cells. Through pyramid size control and morphology treatment, together with the amorphous silicon (a-Si:H) deposition improvement, and electrode optimization, high performance of SHJ solar cells has been achieved, up to conversion efficiency 23.6%.

Investigation of post-annealing effects for normally-off GaN metal-oxide semiconductor heterojunction field-effect transistors with thin AlN barrier layer

The effects of post-annealing processes for normally-off GaN metal-oxide semiconductor heterojunction field-effect transistors (MOS-HFETs) with a thin AlN barrier layer are investigated. These annealing processes are post-deposition annealing (PDA) after oxide deposition, post-metallization annealing (PMA) after gate metallization, and positive-bias annealing (PBA) after wafer processes. PMA and PBA are effective in enhancing the drain current density and threshold voltage shift. The most effective method is PBA and the obtained threshold voltage and drain current density are +3.0 V and 0.7 A mm−1, respectively. This is attributed to improvements in interfacial trap states which is confirmed by an investigation of the frequency dependence of capacitance–voltage characteristics.

Evolution of mechanically formed bow due to surface waviness and residual stress difference on sapphire (0001) substrate

Single crystalline sapphire is one of the most widely used wafers for modern high-technology electronic and optical devices owing to the well-established mass production, own physical properties with high thermal, mechanical, and chemical stability, and lattice constants suitable for growth of highly crystalline films. When single crystalline wafers are used as substrates, the curvature of the wafer surface usually called bow is inevitable. Since bow can degrade the quality of deposited film by defects generation or undesirable strain at the interface, to reduce the bow and surface roughness, procedures such as lapping, annealing, and polishing are followed after wafer slicing. Although single crystalline sapphire has sufficiently high hardness for the device applications, surface waviness after abrasion and residual stress within wafer can induce bow. In this study, we revealed the mechanism of bow evolution using high-resolution X-ray diffraction and Raman spectroscopy following each wafering steps. We found that bow in single crystalline sapphire wafer is mainly determined by the irregularly abraded surface after wafer slicing at earlier wafering process. This kind of bow is significantly reduced after lapping and annealing procedure. However, additional surface polishing can inflict stress on the surface and increase bow due to residual stress difference between the polishing surface and the opposite surface. While bow can be effectively reduced by further polishing on the opposite surface, the surface lattice remains still strained.

Variable Selection Under Missing Values and Unlabeled Data in Semiconductor Processes

Manufacturing semiconductor wafers involves many sequential processes, and each process has various equipment-related variables or factors, which results in high-dimensional data. However, measuring the quality of all wafers is time and cost intensive, and only a small proportion of the wafers is labeled. Further, equipment factors are not always measured by sensors due to the complicated process. Variable selection, which is performed to reduce the dimensionality of the input variable space while improving or preserving regression performance by selecting important input factors, plays an important role in regression problems. We propose a variable selection procedure to find the main equipment factors that affect in-process wafer quality in consideration of the following issues: 1) imputation for missing values; 2) semi-supervised regression for unlabeled data; and 3) redundancy among variables. In the proposed procedure, partial least squares and least absolute shrinkage and selection operator regression are utilized as prediction models. Experiments using two semiconductor equipment datasets were conducted to evaluate the performance of the proposed procedure.

In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers

Device packaging techniques continue to evolve. Modern packages connect components directly using different 3-D interconnect technologies. As the 3-D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect technologies available in 3-D-Stacked IC devices do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer bonding and extreme wafer thinning steps in the 3-D System on Chip integration technology schemes enable the increase of 3-D interconnect density. During the extreme wafer thinning process pathfinding and development, different thinning techniques were evaluated to target a final Si thickness specification. In this paper, metrology use cases that were applied in this pathfinding and development phase are demonstrated. Techniques, such as wafer level interferometry, wafer edge inspection and metrology, wafer front side metrospection, and wafer high resolution topography techniques were used to investigate process issues. Metrology data enabled us to determine where the extreme wafer thinning process could be improved. The same techniques were used to validate the improvements and to monitor process stability.

Key Enabling Materials for 3DIC Fabrication and Device Performance

As the electronics industry reaches the limits of lithographic processing at sub-10nm dimensions, alternate approaches to meet the demand for increasing device density, reducing package size and improving device performance are being explored. Die stacking approaches to reduce the path length between CPU, GPU and memory devices using a heterogeneous 3DIC chip stacking technology have recently been announced, while memory manufacturers have been creating HBM die stacks for use in servers and highspeed applications. At DuPont Electronics & Imaging (E&I), we have been working to enable 3DIC technology through the development of chemicals and processes such as CMP pads and slurries for polishing all the critical materials, chemical cleaners to remove residues, and photoresists to pattern TSVs, pads and pillars. In addition to these materials, E&I also provides permanent materials for hybrid bonding, including electrodeposited copper for TSVs, pads and pillars as well as tin-silver for pillar capping. Another critical part of hybrid bonding is the adhesive bonding material, which needs to be planarized and yet still have sufficient flow to bond at the same time as the Cu-Cu or Cu-SnAg interconnect. This paper will demonstrate how these critical materials can be used together to fabricate 3DIC devices using a conventional bonding tool. Processing of wafers with sub-20 micron pillars has been completed with good metal joining and void-free bonding of the BCB-based polymer adhesive.

熱流体解析によるチップオンウエハにおける熱揺らぎ挙動の定量化

熱流体解析によるチップオンウエハにおける熱揺らぎ挙動の定量化

Auto-Masked Surface Texturing of Kerf-Loss Free Silicon Wafers Using Hexafluoroisopropanol in a Capacitively Coupled Plasma Etching System

As the solar cell industry grows and receives worldwide attention for its sustainability, the consideration for its environmental impact becomes inevitable. The high global warming potential (GWP) of the fluorinated gases commonly used in a plasma processing is a significant environmental issue that needs to be addressed. Substituting the high GWP etchants with alternative gases could be an effective solution in plasma etching. Hexafluoroisopropanol (HFIP) not only has relatively low GWP and short atmospheric lifetime, but is also suitable for forming dense nanostructures on the silicon substrate. The morphology of the nanostructures fabricated on kerf-loss free (KLF) silicon substrates was changed by controlling the DC bias voltage of the capacitively coupled plasma etching system. The resulting reflectance spectra shows that HFIP/O2 plasma etching is highly effective in reducing the optical reflectivity loss of the silicon wafers. The suggested dry processing of KLF silicon wafers could improve both industrial and environmental sustainability of solar cell production.

Investigation of a Standard Particle Deposition System on Wafer Surface and Its Application to Wafer Cleaning

One of the main factors affecting the production yield of semiconductor circuits is contamination by fine particles. Therefore, the wafer cleaning process has become important to the semiconductor manufacturing process. The best method for a cleaning evaluation is to use the actual wafers in the manufacturing process, but where a general cleaning evaluation is required, contaminated wafers cannot be obtained from this source. This study proposes a separate cleaning evaluation wafer as a method for the semiconductor cleaning evaluation. We here describe 300-mm wafers that had nanoparticles of silica (SiO2) and polystyrene latex spheres (PSLs) deposited in multiple designated areas by changing the electric field from 2 kV to 11.2 kV to make spots with diameter from 20 to 50 mm. A numerical analysis was performed to predict the particle trajectory during deposition, and the ensuing experimental results were in good agreement with the simulation, with an average error of 4.2%. Next, some actual wafers were cleaned to demonstrate possible cross-contaminations on the 300-mm wafer, and good effectiveness was achieved. These results provide useful data for optimizing cleaning conditions to improve semiconductor cleaning processes.

Planar cutoff probe for measuring the electron density of low-pressure plasmas

The cutoff probe (CP) is a precise diagnostic technique that measures electron density using two cylindrical probe tips and holders inserted in a low-pressure plasma. However, a recent study has reported that the insertion of the probe tips and holders can perturb the plasma condition and act as a source of error in the measurement of electron density. This study proposes a planar cutoff probe (PCP), which does not have invasive probe tips and holders, to minimize the plasma perturbation during plasma measurement. We embed the PCP on the existing substrate chuck of the plasma chamber instead of inserting an additional probe holder into the chamber. The adjusted conditions for the radii of the probe’s antennas and the gap distance between the two probe antennas are obtained via an electromagnetic simulation. The comparative experiment results show that the inferred electron densities of the optimized PCP are in good agreement with those of the previous CP and within reasonable discrepancies stemming from the differences in measurement positions. We believe that the PCP, which can be embedded in the inner surface of the chamber and measure the electron density during the plasma (wafer) process, would be an alternative technical tool to realize advanced process control of plasma based on non-invasive diagnostic methods.

Collective Cu-Cu Thermocompression Bonding Using Pillars

Abstract The demand for high-performance, high-functionality packages for integrated circuits continues to grow. Three-dimensional (3D) integration is strongly being pursued to meet this demand and has started to reach maturity and industrial adoption. As advanced 3D system designs progress, requiring higher 3D interconnect density with pitches of 10 μm and lower, traditional chip attachment through solder bump technology will likely face complex manufacturing and reliability challenges. Cu-Cu thermocompression bonding has been proposed as a key 3D-enabling technology and alternative to solder. One of the main issues challenging its commercialization in high-volume manufacturing is the sensitivity of Cu-Cu bond quality to prebond surface conditions. This is especially true for die bonding applications which have limited rework options once chips have been singulated. This article outlines further development and demonstration of a tack and collective bonding scheme for Cu-Cu thermocompression bonding. This approach mitigates many of the thermal and throughput issues of a chip-level Cu-Cu attachment process by performing the quick chip alignment at a low temperature and then subsequently completing all Cu bonding simultaneously. The specific use of an intermediate handle wafer between the tack and collective bonding steps allows chips to be reconstructed into a wafer form that facilitates the cleaning and surface preparation of the chips before bonding using standard wafer processing equipment. A chip-to-wafer test structure designed for Cu pillar-to-pad bonding was used as part of this demonstration and illustrates the feasibility of the application. Full transfer of chips to a receiving device wafer using the tack and collective bonding process is shown with electrical test results and selected bond-integrity metrology confirming substantial bond yield and strength.

Scheduling and Control of a Wafer Transfer Robot for Foundry Equipment Innovation Competition

This paper presents a design and implementation of a wafer transfer robotic system for a Foundry Equipment Innovation Competition. In this system, a 4-DOF robotic arm was designed and constructed for wafer transfer between a cassette and processing chambers. The purpose of this competition was to promote intelligent automation for wafer fabrication, in which multiple wafers and chambers need to be handled simultaneously. A scheduling algorithm is proposed for efficient task execution of wafer to process recipes assigned during the competition. The task also features to integrate defect detection and endpoint determination of wafer processing. The robot was required to receive the processing data from the mission platform to determine the endpoint of wafer processing in a chamber and complete the recipe automatically. The online inspection algorithm detects wafer defects during the task execution and report to the task planner. The state of each wafer and chamber are taken into consideration for scheduling in order to complete the wafer fabrication in an efficient and flexible manner. The developed robotic system spent 9 minutes to complete the assigned mission of transferring 6 wafers among multiple chambers and 2 cassettes and achieved 93.4% defect-detection rate in the competition.

Scheduling Dual-Armed Cluster Tools With Chamber Cleaning Operations

Circuit widths and nodes of semiconductor wafers have been continually shrinking down to less than 20 nm. Therefore, modern wafer fabs enforce extremely strict process control to prevent wafer quality failures. A wafer processing chamber is now frequently cleaned to remove residual chemicals and impurities. Yu et al. show that such cleaning operations significantly change the tool operation of single-armed cluster tools, and they suggest an idea of partial wafer loading to improve the tool throughput under cleaning requirements. However, little is known about how a dual-armed tool could be effectively scheduled when chamber cleaning exists. A dual-armed robot allows more flexible tool operational sequences, and hence, the scheduling problem becomes further complicated and challenging. In this paper, we propose a scheduling method by which the dual arms can be properly exploited for better tool productivity. We show that the suggested hybrid sequence significantly reduces the tool cycle time as compared to previously developed scheduling methods. Through this research, we conclude that the productivity gain of the dual arms against single arm is more significant when chambers are cleaned. Note to Practitioners —This paper is motivated by the scheduling issues of cluster tools with chamber cleaning requirements. Though an efficient scheduling method for single-armed cluster tools is presented by Yu et al. , its performance is not sufficiently close to the optimal when a dual-armed robot is considered. More specifically, we cannot expect any productivity improvement from adopting a dual-armed robot, although it allows more flexible tool operations and is known to have higher throughput than a single-armed robot. Thus, we propose a novel scheduling method for dual-armed cluster tools that require chamber cleaning operations. The experimental results show that the suggested method achieves optimal tool throughput in most of the practical tool conditions.

Investigation of Crack Initiation in Glass Substrate by Residual Stress Analysis

To investigate the mechanism of crack initiation in the glass substrate, residual stress in the substrate was analyzed by the finite element method (FEM). A Si wafer that has the same mechanical properties of glass was prepared as the substrate. The thin Cu film layer was fabricated on the Si wafer by plating. The warpage of the wafer in the heat treatment process was investigated by laser displacement measurement. Residual stress was calculated by the obtained warpage value using the Stoney formula. It was found that the warpage becomes zero and the stress-free state occurs around at 150°C. On the basis of the FEM analysis result from 150°C to the room temperature in the cooling process, it was found that analyzed warpage values are almost analogous to measured ones. Also, it was confirmed that equivalent stress in the wafer in the vicinity of the Cu/Si interface increases and the stress-concentrated area expands there with increasing the thickness of the Cu film. The results indicates that crack initiation easily occurs in the glass substrate when the thickness of the Cu film increases. Moreover, from the results of the FEM analysis for the warpage of the wafer in the heating process, it was found that the analyzed warpage is good accordance with the measured one from room temperature to around 150°C.

A Highly Manufacturable 75–150 VDC GaN-SiC RF Technology for Radars and Particle Accelerators

The latest advances in a GaN on SiC RF technology for powering radar systems and particle accelerators are reported. Unlike research-grade technologies based on novel materials, the technology presented here is highly manufacturable as it is based on commercially available GaN on SiC epitaxial wafers and the AlGaN/GaN high electron mobility transistor (HEMT) structure. However, compared to state-of-the-art GaN on SiC RF technology operating from 28 to 50 V, the approach and results presented in this paper explore core transistor designs that are suitable for operation with a bias voltage ranging from 75 to 150 VDC. Wafer processing is similar to typical GaN HEMT process modules for commercially available 28 – 50 V technology and therefore can be easily implemented in existing GaN on SiC manufacturing lines. The approach results in power densities > 10 W/mm at hundred watts power levels which is very desirable in mega-watts RF systems. The results presented in this publication illustrate some of the benefits achievable in radar systems and RF power sources for particle accelerators.

Mechanism and Resolution of Implant Induced Electrical Discharge Damage in GaAs IC

Electrical discharge damage is an unpredictable source of yield loss and a constant challenge to device reliability for the micro-electronics industry. There is considerable history and established methodology for handling charging effects for the silicon semiconductor sector, but literature is generally limited for GaAs and III–V compound semiconductor manufacturing. In this paper, electrical charging and subsequent discharge defects created during isolation implant processing of epitaxial wafers combining hetero-junction bipolar transistor and HEMT are discussed. As is common in semiconductor fabrication, a combination of the circuit layout, process sequence and tool configuration formed the ideal condition for a surge of electrical charging related yield failures. Through extensive examination and analysis, the primary source and mechanism of the failure were identified. These findings lead to development of proper detection and the resolution of the issue through key process improvements that ultimately enhanced yield and the GaAs integrated circuit die robustness against charging induced damage.

Why and How New Japan Radio Has Continued GaAs RFIC Manufacturing in Japan; Introduction of Unique Proven Technology Based on Hetero-Junction FET Process

We describe the history of New Japan Radio Co. Ltd., (NJR) and our continuing presence in the business of manufacturing gallium arsenide radio frequency (GaAs RF) front-end devices. We also explain how our company survived and prospered despite the changing markets. We compare NJR strategies with those of competing RF integrated circuit (RFIC) manufacturers in Japan and briefly describe the hetero-junction field-effect transistor technology, which plays a key role in the success of NJR's RFIC business. We present some of the manufacturing and performance data to show how we improved the wafer process. These unique underlying technologies have enabled the implementation of unique circuit types, which are rarely seen in conventional GaAs ICs.