Wafer-on-Wafer Research Articles

Development of Resins for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration

Development of Resins for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

Low-Temperature Direct Bonding of 3D-IC Packages and Power IC Modules Using Ag Nanotwinned Thin Films

Ag has the lowest stacking fault energy of all metals, which allows twin formation to occur more easily. The (111)-preferred orientation Ag nanotwinned films is fabricated by either sputtering or evaporation method exhibit columnar Ag grains grown vertically on Si substrates. Ag nanotwinned films have a (111)-preferred orientation with a density about 98% and diffusivity that is 2 to 5 orders of magnitude higher than those of (100) and (110) surfaces. Low temperature direct bonding with (111)-oriented Ag nanotwins films is proposed to fulfil the requirements for wafer-on-wafer (WoW), chip-on-wafer (CoW), and chip-on-wafer-on-substrate (CoWoS) advanced 3D-IC packaging, with the process temperature drastically reduced to 100°C. Such an innovative bonding method also provides a promising solution for die attachment of Si chips with DBC-ceramic substrates for power module packaging.

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of the vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both the WOW technology and the leading-edge technologies, is dealt with in this study. Not only 4, 8, and 12 layers, but also 17 (16+1), 25 (24+1), and 33 (32+1) layers can be targeted. Therefore, this technique makes the WOW technology as another system scaling enabler.

(Invited) Trends in 3D Markets and Technology

Driven by performance, 3D packaging with through silicon vias (TSVs) has become a reality for memory and advanced logic. New versions are emerging. High Bandwidth Memory (HBM) is one of the most important 3D IC developments in the last 10 years. In the last decade, stacked DRAM with through silicon vias has transitioned from a handful of research programs to rapidly increasing volumes. Tezzaron has been providing small quantities of 3D ICs for high-speed memory applications since 2005. Micron, Samsung, and SK Hynix began producing DRAM stacks with TSVs in late 2014 and early 2015. Micron began shipments of its Hybrid Memory Cube (HMC) in 2015. DRAMs and the logic controller were interconnected with TSVs. HMC was packaged in a BGA and tested before assembly on the board. The HMC has been used in Intel’s Knights Landing. The silicon-on-insulator (SOI) logic layer was fabricated by GLOBALFOUNDRIES (which purchased IBM’s fab) and the memory was fabricated by Micron. Micron used a thermo-compression bond (TCB) process with a non-conductive film (NCF) underfill for its die stacking in the HMC. Thermal issues were a challenge. Today Samsung and SKHynix are providing HBM stacks to the industry and Micron is expected to ship products next year. In February 2018, Samsung announced that its first “three-layer” stacked CMOS image sensors (CIS) were in mass production and found in the Galaxy S9/S9+. This follows Sony’s adoption of three-layer CIS technology one year earlier in February 2017. A third silicon layer in the form of DRAM is added to the pixel array and signal processing layers to significantly improve data readout speeds. These devices are manufactured with 3D IC technologies using TSVs, but Samsung and Sony use different design approaches. Technically speaking, Samsung’s solution is a two-layer image sensor with a stacked DRAM. Sony uses a true three-layer bonded approach. In its three-layer CIS technology, Sony places the DRAM between the pixel array die and the image processor, with all three layers interconnected using TSVs. The pixel array, DRAM, and logic wafers are manufactured with 90nm, 30nm, and 40nm processes, respectively. While logic and memory stacks have remained elusive, Intel and TSMC have introduced new packaging technology with active interposers that are considered 3D. Intel has introduced its Foveros 3D integration technology as a form of heterogeneous system integration. The technology uses a 3D face-to-face stacking process. In the process, logic die are bumped and mounted on an active interposer next to memory or die with other functions. The active interposer can contain active parts of the system, such as the platform controller hub (PCH) that manages I/O for the system. The active interposer is mounted on a package substrate with solder bumps. TSMC has introduced its SoIC with face-to-face stacking and wafer-on-wafer (WoW). These technologies are front-end packaging and use direct or fusion bonding. The SoIC is a wafer with logic, with our without TSVs.

Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration

This paper develops a bumpless wafer-on-wafer (WoW) memory integration approach in order to increase its throughput and reliability without sacrificing the electrical and mechanical performances compared to the bump-containing chip-on-chip (CoC) integration. The features are that through silicon vias are bottom–up filled after multilayer wafers bonding and connected to the predeposited redistribution layers on the front side of each wafer simultaneously. A given mass of four-layer bumpless WoW integration samples and bump-containing CoC integration samples is fabricated. The electrical testing, X-ray inspection, cross-section observation, stress testing, and thermal cycling testing are employed in order to compare the characterization of the two integration approaches. All test results support that there is a better performance, higher throughput, and lower cost in the proposed bumpless WoW integration approach, which indicates that this proposed approach may be a good candidate for memories-stacking application.

Advances in Wafer Bonding for 3D Integration and Other Applications

Bonding is one of the key technologies that enable the 3D integration. 3D integration has more choices in terms of 3D process flows, such as chip-on-chip (CoC), chip-on-wafer (CoW) or wafer-on-wafer (WoW). Bonding process can be used to glue multiple functional IC chips vertically and provide some combinations of mechanical, thermal, electrical and optical connections between chips or wafers permanently, or to provide temporary mechanical support for wafer thinning and thinned wafer handling. Bonding process also varies with different materials and applications. The choice of bonding technology depends on combinations of the chips and their required process conditions such as temperature limitations. This invited talk focuses on advances in bonding technologies for 3D integration and other applications, including different bonding approaches, requirements for materials and processes, bonding quality characterizations and application-specific bonding technologies.

Observation of lattice spacing fluctuation and strain undulation around through-Si vias in wafer-on-wafer structures using X-ray microbeam diffraction

Spatial fluctuations of the Si 004 lattice spacing, strain, and lattice tilt around through-Si vias (TSVs) in wafer-on-wafer (WOW) structures annealed at different temperatures were quantitatively investigated using X-ray microbeam diffraction. The TSVs were found to induce spatial fluctuations in the base and bonded wafers, and a strain of approximately 0.1% and lattice tilt with a long undulation period of 40 µm were clearly observed. Furthermore, annealing at approximately 100 °C effectively reduced the spatial fluctuation, strain, and lattice tilt in the WOW structure.

Bumpless 접속 기술을 이용한 웨이퍼 레벨 3차원 적층 기술

본 논문은 기존의 미세화 경향에 대한 bumpless through-silicon via (TSV)를 적용한 웨이퍼 레벨3차원 적층기술과 그 장점에 대해 소개한다. 3차원 적층을 위한 박막화 공정, 본딩 공정, TSV 공정별로 문제점과 그 해결책에 대해 자세히 설명하며, 특히 <TEX>$10{\mu}m$</TEX> 이하로 박막화한 로직 디바이스의 특성 변화에 대한 결과를 보고한다. 웨이퍼 박막화 공정에서는 기계적 강도 변동 요인, 금속 불순물에 대한 gettering 대책에 대해 논의되며, 본딩 공정에서는 웨이퍼의 두께 균일도를 높이기 위한 방법에 대해 설명한다. TSV형성 공정에서는 누설 전류 발생 원인과 개선 방법을 소개한다. 마지막으로 본 기술을 적용한 3차원 디바이스에 대한 roadmap에 관해 논의할 것이다. This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than <TEX>$10{\mu}m$</TEX>. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

Bumpless Through-Dielectrics-Silicon-Via (TDSV) Technology for Wafer-Based Three-Dimensional Integration (3DI)

This paper describes wafer-on-wafer (WOW) technology using bumpless through-dielectrics-silicon-via (TDSV) and dual-damascene interconnects for three-dimensional integration (3DI). Trends in conventional scaling compared with bumpless processes, the characteristics of devices after thinning the wafers to less than 10 um, and applications, including closed-channel-cooling systems (C3S), are discussed.

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

In order to realize the manufacturing and cost benefits of bumpless wafer-on-wafer (WOW) technology for the advent of 3D stacked devices, creation of through silicon vias (TSV) spanning all layers of the fully formed semiconductor device must be realized. This is particularly challenging for logic devices with multiple interconnect layers comprised of various dielectric films including low k. This paper, for the first time, demonstrates the manufacture of TSV's through such device's multi-layered dielectric and silicon, simultaneously.

Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

ABSTRACTRecently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.