Abstract
This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of the vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both the WOW technology and the leading-edge technologies, is dealt with in this study. Not only 4, 8, and 12 layers, but also 17 (16+1), 25 (24+1), and 33 (32+1) layers can be targeted. Therefore, this technique makes the WOW technology as another system scaling enabler.
Highlights
T HE bumpless wafer-on-wafer (WOW) technology has significant benefits, including lower vertical interconnect impedance, higher vertical heat conductivity, and the capability to achieve multilayers’ stacking, which are made possible by both an ultrathinning technique and bumpless feature
The known good dies (KGDs) stacking process assembled with the microbump technology gives defect-free silicon die layers, though wafer stacking technology is inevitable due to the probability of randomly defective portions being included in the module stack
We propose a 3-D-manner repair management technique for the WOW technology, in which memory block replacement within the vertical combinations is taken into consideration
Summary
T HE bumpless wafer-on-wafer (WOW) technology has significant benefits, including lower vertical interconnect impedance, higher vertical heat conductivity, and the capability to achieve multilayers’ stacking, which are made possible by both an ultrathinning technique and bumpless feature. Even for the 3-D-stacked DRAM systems, a memory repair process to acquire KGDs is carried out within each layer, that is, in 2-D-manner. We propose a 3-D-manner repair management technique for the WOW technology, in which memory block replacement within the vertical combinations is taken into consideration. In comparison to the current high bandwidth memory (HBM) structure, it will be shown that using this technique, the WOW stacking device will be efficiently produced with yield more than or equal to the KGD stacking device with the 2-D-manner redundancy and will have multilayers’ stacking capability
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