Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Takayuki Ohba,Hiroyuki Ryoson,Koji Sakui,Shinji Sugatani,Norio Chujo

doi:10.3390/electronics11020236

Takayuki Ohba, Hiroyuki Ryoson + Show 3 more

Open Access

https://doi.org/10.3390/electronics11020236

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Abstract

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Highlights

Semiconductor devices and computer systems have evolved as feature sizes have been continuously reduced [1,2,3,4]
Our goal was to yield the maximum number of stacked devices (BBCube) from the total fabricated silicon wafer area of the device
When the single layer die yield Ydevice is greater than or equal to 50%, the Bumpless Build Cube (BBCube) yield becomes more than 99% with 3D redundancy

Summary

Introduction

Semiconductor devices and computer systems have evolved as feature sizes have been continuously reduced [1,2,3,4]. From the late 1990s, 3D technology has been widely studied for the hybrid structure, including package from the die-level to wafer-level, e.g., how to stack semiconductor elements and how to connect between stacked dies with the vertical interconnects such as TSVs [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27] According to this trend, computer system volumes will reach 50 mm, and the power consumption will be 0.5 mW [28,29]. The yield of the wafer stacking case, Y , was calculated from the wafer test yield to the power of the number of stacked layers, k, without any remedy, as expressed in Equation (5)

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