Electrical characteristics of bumpless interconnects for through silicon via (TSV) and Wafer-On-Wafer (WOW) integration

Y S Kim,T.C Hsu,T Ohba,N Maeda,T K Ku,A Kawai,Y Mizushima,S Kodama,P Tzeng,K Fujimoto

doi:10.1109/icep.2016.7486786

Electrical characteristics of bumpless interconnects for through silicon via (TSV) and Wafer-On-Wafer (WOW) integration

Y S Kim, T.C Hsu + Show 8 more

https://doi.org/10.1109/icep.2016.7486786

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Publication Date: Apr 1, 2016

Citations: 13

Affiliation: Tokyo Institute of Technology, Industrial Technology Research Institute, Disco (japan)

#Through Silicon Via #Wafer-On-Wafer + Show 8 more

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Abstract

This paper describes electrical characteristics of bumpless and dual-damascene TSV interconnects for three-dimensional integration (3DI) using Wafer-on-Wafer (WOW) technology. Process optimization counter to integration issues of TSV formation process is demonstrated using test vehicle fabricated with 300-mm wafer and characterized by chain resistance and leakage current in the wafer level.

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