Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform

Abstract

The prospect of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of micro-bumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). The bumpless interconnects technology can increase the number of TSVs per chip with fine pitch of TSVs, and reduce the impedance of the TSV interconnects with no bumps. Therefore, a promising operating platform with a higher speed by enhancing parallelism, lower power by no bumps, and smaller size by thinning wafers, can be realized.