Abstract

Wafer-on-Wafer (WOW) technology for three-dimensional (3D) integration is discussed [1]. Back-to-face wafer stacking using bumpless interconnects and ultra-thinning of wafers are key features used as alternatives to conventional micro-bumps and chip-based stacking technologies [2]–[6]. There is no need for a bump process involving solder bumps and Cu posts for die-to-die internal electronic connections. Ultra-thinning of wafers down to ∼2 µm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of through-silicon-vias (TSVs).

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