High Speed, Low Power, and Ultra-Small Operating Platform with Three-Dimensional Integration (3DI) by Bumpless Interconnects

Abstract

This paper proposes a fundamental architecture for a realization of an ultra-small computing system. The prospect of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of micro-bumps for Wafer-on-Wafer (WOW) technology. The bumpless interconnects technology can increase the number of TSVs per chip with fine pitch of TSVs, and reduce the impedance of the TSV interconnects with no bumps. Therefore, a promising operating platform with a higher speed by enhancing parallelism, lower power by no bumps, and smaller size by thinning wafers, can be realized. By using this technology, the 3D NAND can read and program by plane instead of by line.