Wafer level three-dimensional integration (3DI) using bumpless TSV interconnects for tera-scale generation

Abstract

Bumpless interconnects prospected to the Tera-byte large scale integration using three-dimensional (3D) processes are discussed. The key feature of bumpless as well as no bump interconnects is a second-generation alternative to the use of micro-bump for Wafer-on-Wafer (WOW). Ultra thinning of wafer down to 10 μm provides small form factor not only total volume of 3D ICs but also aspect ratio of Through-Silicon-Via (TSV). In our 3D interconnects technology is classified into Via-Last from the front side after thinning and stacking Back-to-Front in which any number of thinned 300 mm wafers and/or heterogeneous dies. This can be stacked realizing further large-scale devices with low cost rather than the use of extreme ultraviolet (EUV) lithography which will be expected at 18~22 nm and beyond. In the economic sense in many situations, WOW is the leading-edge process among 3D processes because stacking at the wafer level drastically increases the processing throughput and bumpless interconnects provide an appropriate yield using existing technology which is equivalent to or greater than that achievable with 2D scaling beyond 22 nm nodes.