Wafer Level Research Articles

A wafer-level three-step calibration technique for BJT-based CMOS temperature sensor

In order to ensure the consistency of the fabricated devices in batches, calibration is required on CMOS temperature sensor before delivery to compensate the tracking errors of the devices. In the paper, a wafer-level three-step calibration technique for BJT-based CMOS temperature sensor is proposed and fabricated based on TSMC 180-nm-BCD technology. The calibration approach is based on the wafer level, with the simplified calibration process. The strategy of the fuse burning directly maps with the proposed three-step calibration approach. The technique shows encouraging results in removing the error band of the sensor response caused by processing variations in batch fabrication. The calibrated sensor can realize an inaccuracy (±3δ) within ±0.3 °C from −40 °C to 125 °C. The temperature sensor with the calibration module in the paper has great potential application in mobile phones, battery management, disk drives and other fields, etc..

Compact fluidic electrochemical sensor platform for on-line monitoring of chemical oxygen demand in urban wastewater

• Carbon-silica (C/SiO 2 ) thin films produced by sol–gel chemistry. • C/SiO 2 electrode fabrication at wafer-scale by photolithography / etching process. • Excellent electrochemical performance shown by the fabricated electrodes. • Electrochemical sensor integrated in a modular fluidic system for in-field use. • Cu NPs-modified C/SiO 2 sensor used for on-line analysis of COD in urban wastewater. The rapid expansion of urban areas has given rise to the generation of large amounts of wastewater that pose a growing pressure on the surrounding ecosystems. Effective water quality surveillance programs demand the implementation of in-field tests to monitor water safe discharge in the environment after being adequately treated. This paper describes the manufacturing and application of a miniaturized electrochemical sensor for measuring dissolved chemical oxygen demand (COD) in surface waters entering and exiting urban wastewater treatment plants (UWWTP). Thin-film carbon electrodes are produced on Si/SiO 2 substrates by a combined sol–gel material synthesis and photolithography/dry etching process at the wafer level and show superior electrochemical performance compared with the glassy carbon standard electrode. Three-electrode electrochemical cells of planar configuration are produced and the COD sensor is manufactured by electrodepositing copper nanoparticles (Cu NPs) on the working electrode under controlled potentiostatic conditions. A simple fluidic electrochemical sensor device is fabricated and allows for the Cu NPs electrodeposition as well as analytical sensor performance in an automatic fashion. A linear range up to 670 mg·L -1 O 2 and a limit of detection of 30 mg·L -1 O 2 are achieved. The ability of this electrochemical sensor approach to monitoring the soluble organic load of urban wastewater in real-time is evaluated by analyzing three samples collected in different locations of an UWWTP. The COD values estimated with the sensor are in excellent agreement with those obtained using the standard dichromate method provided by an accredited laboratory. This analytical platform provides a robust, user-friendly low-maintenance flow sensor approach for deployed analysis of COD that could aid to control the effectiveness of water treatment processes, especially when facing water influents containing organic overloads due to changing weather conditions or any anthropogenic phenomena.

Machine Vision System Utilizing Black Silicon CMOS Camera for Through-Silicon Alignment

Current development trends concerning miniaturizing of electronics and photonics systems are aiming at assembly and 3-D co-integration of a broad range of technologies including MEMS, microfluidics, wafer level optics, and silicon photonics. To this end, on-chip integration using silicon-photonics platform offers a wide range of possibilities addressing passive optics functionality, active optoelectronic devices, and compatibility with CMOS fabrication. On the other hand, the hybrid technology enabling volume manufacturing of such system-on-chip components, it is still in an early development stage. Here, a new type of machine vision system enabling precision stacking and bonding processes of III–V components on silicon photonics chips is introduced. In particular, we focus on the ability to see through substrates with high resolution, which is crucial for the alignment of the markers used for assembly of integrated components on silicon wafer. The system is based on the use of a black silicon enhanced CMOS sensor with extended wavelength response beyond transparency cutoff wavelength for silicon substrate. We study the use of the camera system as a microscope with bottom coaxial infrared (IR) illumination scheme and demonstrate the ability of through-silicon vision for one- and two-layered silicon photonic integrated circuit (PIC) samples. The ability of observing objects with dimensions down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 \mu \text{m}$ </tex-math></inline-formula> is confirmed. This resolution is close to diffraction limit and corresponds to the dimensions of optical waveguide structures on the PICs surface. In addition, we demonstrate the implementation of a 2-D Fourier transform-based autofocusing technique for through-silicon IR microscopy. These building blocks offer a solution for advanced photonic integration processes and other through-silicon vision-related applications, which is instrumental for a large variety of assembly, lithography, and wafer bonding setups.

Design of a High Sensitivity Pirani Gauge Based on Vanadium Oxide Film for High Vacuum Measurement

We have designed a hot-plate-type micro-Pirani vacuum gauge with a simple structure and compatibility with conventional semiconductor fabrication processes. In the Pirani gauge, we used a vanadium oxide (VOx) membrane as the thermosensitive component, taking advantage of the high temperature coefficient of resistance (TCR) of VOx. The TCR value of VOx is -2%K-1∼-3%K-1, an order of magnitude higher than those of other thermal-sensitive materials, such as platinum and titanium (0.3%K-1∼0.4%K-1). On one hand, we used the high TCR of VOx to increase the Pirani sensitivity. On the other hand, we optimized the floating structure to decrease the thermal conductivity so that the detecting range of the Pirani gauge was extended on the low-pressure end. We carried out simulation experiments on the thermal zone of the Pirani gauge, the width of the cantilever beam, the material and thickness of the supporting layer, the thickness of the thermal layer (VOx), the depth of the cavity, and the shape and size. Finally, we decided on the basic size of the Pirani gauge. The prepared Pirani gauge has a thermal sensitive area of 130 × 130 μm2, with a cantilever width of 13 μm, cavity depth of 5 μm, supporting layer thickness of 300 nm, and VOx layer thickness of 110 nm. It has a dynamic range of 10-1~104 Pa and a sensitivity of 1.23 V/lgPa. The VOx Pirani was designed using a structure and fabrication process compatible with a VOx-based uncooled infrared microbolometer so that it can be integrated by wafer level. This work contains only our MEMS Pirani gauge device design, preparation process design, and readout circuit design, while the characterization and relevant experimental results will be reported in the future.

Ultrasensitive dopamine detection with graphene aptasensor multitransistor arrays

Detecting physiological levels of neurotransmitters in biological samples can advance our understanding of brain disorders and lead to improved diagnostics and therapeutics. However, neurotransmitter sensors for real-world applications must reliably detect low concentrations of target analytes from small volume working samples. Herein, a platform for robust and ultrasensitive detection of dopamine, an essential neurotransmitter that underlies several brain disorders, based on graphene multitransistor arrays (gMTAs) functionalized with a selective DNA aptamer is presented. High-yield scalable methodologies optimized at the wafer level were employed to integrate multiple graphene transistors on small-size chips (4.5 × 4.5 mm). The multiple sensor array configuration permits independent and simultaneous replicate measurements of the same sample that produce robust average data, reducing sources of measurement variability. This procedure allowed sensitive and reproducible dopamine detection in ultra-low concentrations from small volume samples across physiological buffers and high ionic strength complex biological samples. The obtained limit-of-detection was 1 aM (10–18) with dynamic detection ranges spanning 10 orders of magnitude up to 100 µM (10–8), and a 22 mV/decade peak sensitivity in artificial cerebral spinal fluid. Dopamine detection in dopamine-depleted brain homogenates spiked with dopamine was also possible with a LOD of 1 aM, overcoming sensitivity losses typically observed in ion-sensitive sensors in complex biological samples. Furthermore, we show that our gMTAs platform can detect minimal changes in dopamine concentrations in small working volume samples (2 µL) of cerebral spinal fluid samples obtained from a mouse model of Parkinson’s Disease. The platform presented in this work can lead the way to graphene-based neurotransmitter sensors suitable for real-world academic and pre-clinical pharmaceutical research as well as clinical diagnosis.

Laser Lift‐Off Technologies for Ultra‐Thin Emerging Electronics: Mechanisms, Applications, and Progress

AbstractDue to the advantages of non‐contact processing, high efficiency, high precision, and superior controllability, laser lift‐off (LLO) technologies exhibit excellent material applicability and process compatibility in the lift‐off of ultra‐thin electronic devices. This brings new opportunities for large‐scale manufacturing of emerging electronics that meet ultra‐thin, fragile, and poor high‐temperature resistance. However, this opportunity also comes with formidable challenges from the complex mechanisms of laser‐matter interactions, which hinder comprehensive exploration and fundamental understanding. By elaborating the laser‐material interactions, the photothermal effect, “cold” processing, shockwave effect, and cavitation effect in LLO process from multiple perspectives, this review is devoted to discussing the latest progress and sustainable application of LLO technologies in emerging electronics that are developing toward ultra‐thin, miniaturization, and integration, such as wafer level packaging, displays, energy harvesters, sensors, and memories. Finally, starting from the fundamental principles of material design, light field regulation, and intelligent control system, the challenges and new approaches faced by LLO technologies are explored and fully integrated with future innovative manufacturing concepts and device structures.

From Lab-on-chip to Lab-in-App: Challenges towards silicon photonic biosensors product developments

This work presents and evaluates different approaches of integrated optical sensors based on photonic integrated circuit (PIC) technologies for refractive index sensing. Bottlenecks in the fabrication flow towards an applicable system are discussed that hinder a cost-effective mass-production for disposable sensor chips. As sensor device, a waveguide coupled micro-ring based approach is chosen which is manufactured in an 8” wafer level process. We will show that the co-integration with a reproducible, scalable and low-cost microfluidic interface is the main challenge which needs to be overcome for future application of silicon technology based PIC sensor chips.

Solderability and Reliability of Sintered Nano-Ag Bond Pads of Printed Re-Distribution Layer

Abstract Redistribution layer (RDL) is one key enabling technology for advanced packaging. RDL is usually fabricated at wafer level by a photolithography process. An alternative approach for implementing RDL by additive manufacturing (AM) method is proposed in this study. This allows RDL to be fabricated on a singulated chip. Nanosilver (nano-Ag) ink is printed on the silicon chip to form routing traces and bond pads. However, the Ag pad may be consumed by the solder quickly if the reflow process is not properly controlled. The mechanical integrity of the solder joint was evaluated by both solder ball shear and die shear tests. A high temperature storage test and humidity test were carried out to evaluate the solder joint reliability. Experiment results showed that the Ag pad fabricated by AM is compatible with surface mount technology (SMT). Reliable solder joints on the Ag pad were achieved. There was no significant change in the Ag3Sn intermetallic compound (IMC) layer thickness and mechanical strength after aging at high temperature and high humidity conditions. There was no early solder joint failure observed. The finding of the present study will serve as a very useful reference for the future practice of forming solder joints on sintered nano-Ag pads.

Controlled Thermal Imidization of Thermoplastic Polyimide for Temporary Bonding and Debonding in Advanced Packages

Temporary bonding and debonding (TBDB) is a key technology in the semiconductor field to enable 2.5D/3D integration of devices. However, the conventional polyimides, which serve as the laser-response material in TBDB, exhibit extremely poor solubility in aprotic polar solvents due to high-temperature imidization, limiting the cleaning process for wafers after debonding. Herein, a feasible method of controlling the curing temperature to enhance the solubility of thermoplastic polyimide (TPI) has been developed. The results proved that the ultimate solubility of TPI cured at 200 °C (TPI-200 °C) could be as high as 28.4 wt %. Besides, TPI-200 °C exhibits excellent heat resistance, outstanding mechanical properties, and ultrahigh absorptivity (99.96%) at a 355 nm UV wavelength. Meanwhile, we demonstrate the feasibility of the as-prepared TPI material for application in the TBDB process, showing excellent efficiency and low cost, and the follow-up elemental analysis of the cleaned wafer surfaces proved that TPI-200 °C can be completely removed after debonding. All these results demonstrate that TPI materials that can be used for TBDB are promising for ultrathin chip packaging and wafer level packaging (WLP) in the field of advanced electronic packaging.

Wafer level response to mask deficiencies in 0.55-numerical aperture extreme ultraviolet photolithography

BackgroundThis study investigates the impact of 0.55-numerical aperture (NA) imaging on wafer defectivity when multilayer ripple is present in the extreme ultraviolet (EUV) mask.AimWe investigate the impact of 0.55-NA anamorphic imaging on one-dimensional (1D) and two-dimensional (2D) horizontal and vertical mask feature deficiencies on wafer defectivity. The information in the study is intended to guide experimentation to aid in setting standards for EUV mask blanks in 0.55-NA lithography.ApproachThis study stochastically simulated 1D and 2D horizontal and vertical features using an extreme ultraviolet mask with varied random multilayer ripple configurations. The photoresist critical dimension (CD) was measured from the simulated wafer and used to generate statistical analysis of the simulation.ResultsHorizontal 1D features show an ∼2.5 × improvement in failure ratio versus vertical 1D features. Vertical 2D features appear to have a lower failure ratio compared with 2D horizontal features, but the difference is not as clear as found in the 1D case. The light scattered from the leaf shaped illuminator into the pupil background region due to multilayer ripple from 2D features appears smaller than in the 1D case. Potentially mask deficient structures may benefit from orientating the CD vertically on an anamorphic system to reduce wafer level defectivity.ConclusionsThere appears to be a multilayer ripple saturation level for 1D and 2D features at which defectivity and CD variation become constant. Horizontal imaging appears to be preferable for all CDs. The roughness threshold computational shortcut to mask deficiency characterization may not be sufficient for 2D features. The 2D analysis in this study does not change previous mask standard suggestions.

Generation of spin currents by the orbital Hall effect in Cu and Al and their measurement by a Ferris-wheel ferromagnetic resonance technique at the wafer level

We present a new ferromagnetic resonance (FMR) method that we term the Ferris FMR. It is wideband, has significantly higher sensitivity as compared to conventional FMR systems, and measures the absorption line rather than its derivative. It is based on large-amplitude modulation of the externally applied magnetic field that effectively magnifies signatures of the spin-transfer torque making its measurement possible even at the wafer-level. Using the Ferris FMR, we report on the generation of spin currents from the orbital Hall effect taking place in pure Cu and Al. To this end, we use the spin-orbit coupling of a thin Pt layer introduced at the interface that converts the orbital current to a measurable spin current. While Cu reveals a large effective spin Hall angle exceeding that of Pt, Al possesses an orbital Hall effect of opposite polarity in agreement with the theoretical predictions. Our results demonstrate additional spin- and orbit- functionality for two important metals in the semiconductor industry beyond their primary use as interconnects with all the advantages in power, scaling, and cost.

Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology

During the last decade optical sensor technologies have attracted increased attention for various applications. Plasmon-based optical sensor concepts for the detection of refractive index changes that rely on propagating surface-plasmon polaritons at metal-dielectric interfaces or on localized plasmons in metallic nanostructures prove their potential for these application due to their fast detection speed, high specificity and sensitivities [1, 2]. Combining plasmonic structures directly with optoelectronic devices could enable a high level of integration, however, it represents a significant technological challenge to develop an on-chip solution for these concepts including the integration of sensor and detector components. Previous works demonstrated first approaches mainly for the integration of refractive index sensor components on wafer level [3, 4]. In [5] and [6] a proof-of-concept of a fully integrated on-chip solution with high sensitivities was presented, which can be easily combined with microfluidics [7] for potential applications in biosensing. In this concept, a nanohole array (NHA) was structured in a 100 nm thick aluminum layer on top of a vertical PIN germanium photodetector (GePD) with an intrinsic germanium sheet of 480 nm. This sensor concept relies on extraordinary optical transmission through the NHA [8]: Light transmission is only possible for narrow wavelength ranges determined by the NHA geometry which determine the transmission peaks at the resonance wavelength of the NHA. Thus, the NHA acts as a high quality wavelength filter. Due to the change in the refractive index, a material under test (MUT) contacting directly the surface of the NHA, provokes a shift of the wavelength maximum, which can be detected by measuring the photocurrent spectra of the GePD. While responsivities and sensitivities of (0 V) = 0.075 A/W and = 1200 nm/RIU could be attained in this proof-of-concept device [6, 7], the semiconductor device layers were deposited using molecular beam epitaxy (MBE). Furthermore the vertical PIN GePD was realized by a mesa procedure to enable large areas for top illuminated operations. These techniques are unsuitable for an industrial CMOS fabrication process with high throughput. Therefore, the development of a CMOS compatible technology process with low costs and high yields is an important step towards large-scale fabrication of this sensor concept.In this work we present the progress for the realization of a surface plasmon resonance (SPR) refractive index sensor in a 200 mm wafer Silicon based technology. One main challenge is the fabrication of a large area photodetector for top illuminated sensor devices. We developed a process, which is mainly based on the IHP electronic photonic integrated circuits (ePIC) technology [9]. This ePIC technology enables the production of waveguide coupled lateral PIN GePDs with high bandwidth and high responsivities [10]. However, these PDs are unsuitable for top illuminated applications because of their small germanium areas. Due to certain process conditions with respect to chemical mechanical polishing procedures there are limits for feasible large detector areas. Furthermore, large detector areas for lateral PIN GePDs would result in very low electric fields in the intrinsic zone where carriers are generated by photon absorption. Thus, very high voltages for reversed bias are necessary for sufficient carrier drifts.For the first time we have developed a modern detector design concept which is compatible to the IHP ePIC technology. This concept allows the realization of large area detectors of 1600µm² (40µm x 40µm) with optimized optical responsivities for top illuminated applications. The detector consists of several parallel connected lateral PIN GePDs. We designed different variations and varied Ge width and distance between neighboring GePDs in order to investigate process limits. The p- and n-doped regions were defined by dopant implantation using a photo resist mask. We used a finger-like design as implantation masks to enable one contact area for each p-doped and each n-doped region (Fig. 1). This contacting approach differs from the standard GePD offered in the IHP ePIC technology. We analyzed I-V characteristics in dependence of detector design and contacting scheme (Fig. 2). In addition, process adjustments for the optimization of the germanium quality were investigated to reduce dark currents and to improve optical responsivities (Fig.3).Titanium nitride (TiN) is very promising metallic alloy with respect to thickness homogeneity and low surface roughness. Therefore we used titanium nitride which was deposited by a sputtering process to develop plasmonic active NHA layers. Various process development runs were done to evaluate the NHA performance. Ellipsometry and atomic force microscope measurements were performed to characterize the quality of the TiN layer (Fig.4). Figure 1

(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems

Fan-out wafer-level packaging has become during the last decade an iconic part of the More Than Moore trend. Emerging in the mid-2000s and early declined in embedded wafer level ball grid array (eWLB), it has since gained popularity for the realization of high-potential systems-in-package (SiP).The basic technology is based on the reconstruction of wafers from individual chips. After embedding chips with an epoxy mold compound (EMC), electrical connections are processed in the form of redistribution layers (RDL) to fan-out signals from chip I/Os to solder balls, whose dimensions are compatible with direct soldering to a printed circuit board. Eliminating the need for intermediate laminated substrates, it has enabled the integration of systems with high performance at reduced cost and footprint. It has also paved the way for applications that would have been difficult to address with conventional packaging.In a resolutely heterogeneous declination of this technology, the co-integration of several chips in a single and dense package has allowed processing multi-chip SiPs including CMOS circuits, memories, radio-frequency (RF) chips and passive components with reduced interconnect length. It is indeed possible to combine in the same package different materials such as Si, SiC, GaN, AsGa. This property gives FOWLP technology unique advantages in terms of cost and versatility that make it attractive in many application areas.Two trends seem to take advantage of this technology. On one hand, the realization of high performance SiPs integrating miniaturized CMOS processors and dense, high bandwidth memories with aggressive interconnects design rules. On the other hand, highly heterogeneous systems mixing semiconductors, especially in the field of wireless telecommunications. For over a decade, RF devices have been taking advantage of FOWLP to build advanced packages with shorter interconnects. Mass production has been reached since 2009 for automotive radars, baseband processors, RF transceivers and power management circuits. More recently, the millimeter wave market has gained interest with the development of 5G at high frequencies (>6 GHz), where the fan-out area becomes an opportunity to embed high quality passives and antennas.CEA-Leti has been studying this technology from its inception, with pioneering work since 2005 outlining wafer reconstruction for heterogeneous integration. At the heart of integration, the epoxy mold compound (EMC) is the way to reconstruct the wafer. By becoming the mechanical link between the different chips, it plays a crucial role during the entire process. On another level, the interconnects constitute the final purpose of the FOWLP integration: RDL layers create the link between chips in heterogeneous SiPs, as well as the link between the SiP and the outside world. These two components must be mastered to ensure functionality and performance of final SiPs.Among various available configurations, the die first scheme consists in positioning chips before molding and processing the interconnects. In RDL 1st scheme the interconnections are, conversely, made before chips are placed. Although these approaches sometimes compete, they generally meet different specifications. Nevertheless, all the configurations share integration issues related to the materials and processes involved. Some of the classic issues met in FOWLP include wafer deformation due to CTE mismatches, die shift during the process and the difficult task of heat dissipation in dense SiPs with increased power densities. We will show how useful the characterization techniques are to develop and improve the overall process, in order to reach the targeted specifications.To illustrate these elements, a detailed description of the technology built up for the realization of heterogeneous systems will be given, such as 5G base stations transceiver operating at 28 GHz including GaN and AsGa chips. We will also present original options implemented to meet the needs of other application fields, and develop our strategy regarding thermal dissipation for future SiPs.In a FOWLP approach, three-dimensional integration is also possible thanks to a technological toolbox that includes, in addition to RDL and solder balls, vertical connections such as Through-Mold Via (TMV). We will describe an original approach developed at CEA-Leti for the fabrication of high aspect ratio TMVs, with a demonstration of 225 µm high and 100 µm pitch TMV for the realization of 3D SiP with high interconnection density. Figure 1

W-band antenna in package module with hybrid glass-compound WLFO process

PurposeA W-band antennas-in-packages (AIP) module with a hybrid stacked glass-compound wafer level fan-out process was presented. Heterogeneous radio frequency (RF) chips were integrated into one single module with a microscale fan-out process. This paper aims to find a new strategy for 5G communication with 3D integration of multi-function chips.Design/methodology/approachThe AIP module was composed of two stacked layers: the antenna layer and RF layer. After architecture design and performance simulation, the module was fabricated, The 8 × 8 antenna array was lithography patterned on the 12 inch glass wafer to reduce the parasitic parameters effect, and the signal feeding interface was fabricated on the backside of the glass substrate.FindingsAIP module demonstrates a size of 180 mm × 180mm × 1mm, and its function covers the complete RF front-end chain from the antenna to signal to process and can be applied in 5 G communication and automotive components.Originality/valueWith three RF multi-function chips and two through silicon via (TSV) chips were embedded in the 12 inch compound wafer through the fan-out packaging process; two layers were interconnected with TSV and re-distributed layers.

Package-level Joule-heating measurements for multilevel interconnects

Interconnect warming and temperature-gradient effect on chip performance and reliability are key topics of interest both for aluminium (Al) and copper (Cu) interconnects. For more demanding electromigration (EM) Idc specifications, it is essential to take the Joule-heating effect into account. In this paper, we present package-level Joule-heating characterisation results for Al-based interconnects. A comparison with Joule-heating measurements at wafer level is also presented. The root-mean-square (RMS) current-specification limits, Irms, obtained from wafer- and package-level measurements are compared with the values obtained from the pseudo-1D heat-dissipation equation. Different metal layers with various metal widths are studied. The results indicate that Joule heating at package level is higher compared to wafer level, which restricts the allowed Irms at package level. For wide lines in the lower metal layers, a deviation from the pseudo-1D model is observed in package-level measurements. While Irms limits are generally based on the pseudo-1D model, this study motivates further evaluation of interconnect reliability by determining realistic self-heating generated by package-level measurements.

Achieving low-temperature wafer level bonding with Cu-Sn-In ternary at 150 °C

In this work, a low-temperature wafer-level bonding process at 150 °C was carried out on Si wafers containing 10 µm-sized microbumps based on the Cu-Sn-In ternary system. Thermodynamic study shows that addition of In enables low-melting temperature metals to reach liquid phase below In melting point (157 °C) and promotes rapid solidification of the intermetallic layer, which are beneficial for achieving low-temperature bonding. Microstructural observation shows high bonding quality with low amount of defect. SEM and TEM characterization concludes that a single-phase intermetallic formed in the bond and identified as Cu6(Sn,In)5 with a hexagonal lattice. Mechanical tensile test indicates that the bond has a mechanical tensile strength of 30 MPa, which are adequate for 3D heterogeneous integration.

Defect detection on optoelectronical devices to assist decision making: A real industry 4.0 case study

This paper presents an innovative approach, based on industry 4.0 concepts, for monitoring the life cycle of optoelectronical devices, by adopting image processing and deep learning techniques regarding defect detection. The proposed system comprises defect detection and categorization during the front-end part of the optoelectronic device production process, providing a two-stage approach; the first is the actual defect identification on individual components at the wafer level, while the second is the pre-classification of these components based on the recognized defects. The system provides two image-based defect detection pipelines. One using low resolution grating images of the wafer, and the other using high resolution surface scan images acquired with a microscope. To automate the entire process, a communication middleware called Higher Level Communication Middleware (HLCM) is used for orchestrating the information between the processing steps. At the last step of the process, a Decision Support System (DSS) collects all information, processes it and labels it with additional defect type categories, in order to provide recommendations to the optoelectronical engineer. The proposed solution has been implemented on a real industrial use-case in laser manufacturing. Analysis shows that chips validated through the proposed process have a probability to lase at a specific frequency six times higher than the fully rejected ones.

Nonevaporable getter-MEMS for generating UHV conditions in small volumina

The industrial use of quantum sensors requires further miniaturization of the experimental peripherals, i.e., the high vacuum chamber, laser technology, and control electronics. A central part of the high vacuum chamber is the maintenance of vacuum conditions. For this purpose, a prototype of a compact, i.e., miniaturized, ultrahigh vacuum pump in the form of a nonevaporable getter (NEG) pump at a wafer level (MEMS), is developed within the scope of this work. With regard to the basic conditions of the functionality of the NEG, a miniaturized heating plate with temperature sensors is analytically and numerically developed, constructed, and characterized in an ultrahigh vacuum test stand. This is followed by the integration of the NEG into the existing system, which, in connection with the characterization of material-specific parameters, enables a first correlation of heat input and pumping power. Thus, performance data of the getter-MEMS under high-vacuum confinement confirm its usability for quantum sensors. In addition, optimization potentials are shown with regard to all partial aspects of the MEMS.

Suppression strategy for process-induced warpage of novel fan-out wafer level packaging

In the study, the novel fan-out wafer level packaging (FOWLP) technology is presented in which the through silicon via (TSV) array interposer layer is manufactured. Compared to conventional FOWLP technology, the present novel FOWLP technology has several advantages of better signal integrity, higher electrical performance, and easier customization. However, similar to the conventional FOWLP technology, the process-induced warpage resulted from the mismatch of the coefficient of thermal expansion (CTE) among the constituent materials is also an essential issue during the fan-out fabrication process, which is notably for successful process integration. This study proposes a comprehensive assessment of the process-induced warpage of the novel FOWLP during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis incorporated with the element death-birth technique. The study starts from establishing a silicon interposer layer with TSV array, attachment of glass carrier, multiple redistribution layers (RDLs), and dielectric layers. The warpage evolution during the fan-out fabrication process is thoroughly evaluated according to the temperature loading profile. To demonstrate the effectiveness of the proposed theoretical model, the novel FOWLP test vehicle is manufactured for experimental measurement. Finally, the parametric study together with response surface methodology is further applied to provide guidelines for suppressing the warpage. Overall, the simulation modeling represents a feasible approach for predicting the process-induced warpage during the fan-out fabrication process.

Wide bandgap semiconductor nanomembranes as a long-term biointerface for flexible, implanted neuromodulator

Electrical neuron stimulation holds promise for treating chronic neurological disorders, including spinal cord injury, epilepsy, and Parkinson's disease. The implementation of ultrathin, flexible electrodes that can offer noninvasive attachment to soft neural tissues is a breakthrough for timely, continuous, programable, and spatial stimulations. With strict flexibility requirements in neural implanted stimulations, the use of conventional thick and bulky packages is no longer applicable, posing major technical issues such as short device lifetime and long-term stability. We introduce herein a concept of long-lived flexible neural electrodes using silicon carbide (SiC) nanomembranes as a faradic interface and thermal oxide thin films as an electrical barrier layer. The SiC nanomembranes were developed using a chemical vapor deposition (CVD) process at the wafer level, and thermal oxide was grown using a high-quality wet oxidation technique. The proposed material developments are highly scalable and compatible with MEMS technologies, facilitating the mass production of long-lived implanted bioelectrodes. Our experimental results showed excellent stability of the SiC/silicon dioxide (SiO2) bioelectronic system that can potentially last for several decades with well-maintained electronic properties in biofluid environments. We demonstrated the capability of the proposed material system for peripheral nerve stimulation in an animal model, showing muscle contraction responses comparable to those of a standard non-implanted nerve stimulation device. The design concept, scalable fabrication approach, and multimodal functionalities of SiC/SiO2 flexible electronics offer an exciting possibility for fundamental neuroscience studies, as well as for neural stimulation-based therapies.