Wafer Level Research Articles

Wafer level quasi-van der Waals epitaxy of AlGaN/GaN heterojunctions on sp2-bonded BN controlled by AlN nucleation layer

Two dimensional materials, such as sp2-bonded boron nitride (BN) and graphene, have been proven to be excellent templates for the growth and fabrication of independent group III-nitride materials. Herein, wafer level sp2-bonded BN film was successfully grown as a release layer on two-inch sapphire substrate using MOCVD. The different nucleation mechanisms of gallium nitride (GaN) and aluminum nitride (AlN) grown on the BN surface were investigated. We discovered that AlN has a higher nucleation island density compared to GaN on the surface of BN which facilitates better merging of the GaN epitaxial layer. In addition, the quality of the GaN epitaxial layer was optimized by adjusting the growth temperature of AlN. A complete AlGaN/GaN heterojunction structure was subsequently grown on the best quality of GaN, and its average mobility and interlayer carrier concentration was about 1600 cm2 V−1 s−1 and 1 × 1013 cm−2. Finally, the AlGaN/GaN heterojunction was easily transferred from the substrate using tape, which proved the good 2D characteristics of sp2-bonded BN and can undergo non-destructive van der Waals transfer for the upper layer device.

A 3D tailored monolithic glass chip for stimulating and recording zebrafish neuronal activity with a commercial light sheet microscope

Microfluidic technology is unrivaled in its ability to apply soluble chemical stimuli with high spatiotemporal precision. Analogous, light–sheet microscopy is unmatched in its ability of low phototoxic but fast volumetric in vivo imaging with single cell resolution. Due to their optical translucency during the larval stages, zebrafish (Danio rerio) are an ideal model to combine both techniques; yet, thus far this required light–sheet microscopes, which were in most cases custom–built and adapted to the available softlithographic chip technology. Our aim was to use a commercial light–sheet microscope to illuminate a microfluidic chip from two opposite lateral directions and to record images with the detection objective placed orthogonally above the chip. Deep tissue penetration can be achieved by superimposing beams from opposite directions to form a single light sheet. But a microfluidic chip that allows a) targeted stimulus application in a closed microenvironment, b) interference–free incoupling of excitation light from two directions and c) outcoupling of fluorescence in the perpendicular direction through an optically perfect cover glass was not known until now. Here, we present a monolithic glass chip with the required plane-parallel sidewalls and cover slide closure at the top, constructed by advanced femtosecond laser ablation, thermal bonding and surface smoothing processes. In addition, the 3D shape of a fish fixator unit was tailored to match the body shape of a zebrafish larva to ensure stable positioning during whole–brain recording. With hydrodynamic focusing a targeted partial exposure of the larva’s head to chemical stimuli and fast position switching (in less than 10 s) was possible. With the capabilities of this unique monolithic glass chip and its up–scalable wafer–level fabrication process, the new NeuroExaminer is prone to become an excellent addition to neurobiology laboratories already equipped with high–quality commercial light sheet microscopes.

Deposition of Fine-Pitch Indium Bumps on Single Die

Photolithographic lift-off at wafer level is a wellestablished method for depositing indium bumps onto pixels of electronic components such as sensors and application-specific integrated circuits (ASIC). These indium bumps form interconnects between pixels of the components during flip-chip bonding to make devices such as radiation detectors. Such components are not always available on wafer-scale, and single dies need to be processed in small-scale production, R&D, or for Cd(Zn)Te detector material. Photolithography on single dies is ineffective due to the edge-bead of photoresist that compromises perfect indium deposition onto pixels near the periphery of the die. To utilize the maximum surface area of a die, a rigid mask with apertures (shadow mask) is an adequate substitute for the photoresist. Different mask designs and production techniques for fine-pitch indium bump arrays are investigated by testing electroformed stencils or micromachined silicon (Si) membranes as shadow masks. For the indium deposition, the sensor and ASIC dies are clamped into custom-made jigs that include shadow masks. Alternatively, dies can be adhered to shadow masks with soluble adhesive. The apertures of a mask are aligned to the pixel array of the detector component. Bump arrays with 250μm- and 100μm-pitch were demonstrated with electroformed stencils. For smaller pitch (55μm) and bump diameter of ~20μm, specialized masks from Si membranes are tested. Components with successfully deposited indium bump arrays were subsequently flip-chip bonded at room temperature without reflowing the indium. A bond yield of at least 99.9% pixels for such flip-chip bonded radiation detector was shown using the read-out signal from exposure with a flat field X-ray radiation of an Am-241 sealed source.

Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging

In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is generated in those layers due to curing shrinkage of the polyimide and the coefficient of thermal expansion mismatch of both materials to silicon which can lead to severe wafer bow after a high temperature curing. In different applications polyimide can be used either only as passivation layer over electroplated copper, or polyimide is applied before the redistribution layer and then a second polyimide layer is applied as passivation. In the current study the effect of different polyimide integrations is investigated. In-situ wafer bow measurements and finite element method studies were conducted with samples, with and without polyimide below redistribution layer, exposed to different curing temperatures to understand the change in wafer bow and copper residual stress. It is observed that wafers with polyimide before redistribution layer show higher stress relaxation in copper with decreasing curing temperature, resulting therefore in a lower wafer bow. A good agreement is achieved between the experimentally measured and the simulated wafer bow.

Laser-Assisted Bonding Approach for Photonic Integration Processes

Current development trends concerning miniaturizing of electronics and photonics systems are aiming at assembly and 3D co-integration of a broad range of technologies including MEMS, microfluidics, wafer level optics, and silicon photonics. To this end, on-chip integration using siliconphotonics platform offers a wide range of possibilities addressing passive optics functionality, active optoelectronic devices, and compatibility with CMOS fabrication. On the other hand, the hybrid technology enabling volume manufacturing of such system-on-chip components it is still in an early development stage. In this work, the original LAB setup with a coaxial bottom irradiation architecture was developed. The setup allows a rapid and energy-effective process with the ability to produce successful electrical bonds with negligible thermalinduced stress and warpage to bonded surfaces. The proposed machine-vision based temperature sensor is validated for photonic integration assembly processes.

Broadband packaging solution in embedded wafer level ball grid array technology for D-band PMCW radar

Abstract A system-in-package for a wideband digital radar, in D-band, requires broadband, high-gain antennas combined with broadband chip-to-package and package-to-printed circuit board (PCB) interconnects. This paper demonstrates a wideband, low-loss quasi-coaxial signal transition, and a novel electric split ring resonator (eSRR)-based antenna-in-package (AiP) with a modified reflector concept, for improved gain, in embedded wafer level ball grid array (eWLB) technology. A complete chip-to-package-to-PCB interconnect is also demonstrated by combining the quasi-coaxial transition with a chip-to-package interconnect. The quasi-coaxial signal transition has the largest impedance bandwidth among ball grid array-based quasi-coaxial signal transitions. For the modified reflector concept, a horn-shaped cavity is micromachined in the PCB substrate and remetallized with aerosol-jet printing, placing the reflector 0.25λ from the antenna. The antenna gain is improved with up to 5.3 dB. The AiP with the horn-shaped reflector is the single element with the highest gain, in eWLB technology, above 100 GHz.

Characterizations for eWLB (Embedded Wafer Level Ball Grid Array) Antenna in Molded Package Integrations in 77GHz Automotive Applications

The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing, consumer, automotive, industrial, etc. Among these market segments, the automotive market is forecast to have the strongest CAGR (Compound Annual Growth Rate) of any of the end-use segments in the next 5 years, which results in more IC packages and components being designed into automotive vehicle systems such as infotainment, ADAS (Advance Driving Assistance System), instrumentation, body systems, battery control systems and so on. In these applications, the 77GHz short-range radar sensor application that can enable higher EIRP (Effective Isotropic Radiated Power) and adaptive cruise control performance has become more attractive to be commercialized. Due to the benefits of shorter interconnection length, lower conductive loss with smooth Cu surface as well as a lower dielectric constant and dielectric loss of materials in a fan-out wafer level package (FOWLP) technology, the FOWLP is proven as a suitable packaging solution to achieve the high speed and frequency requirements in 5G and mmWave applications. The eWLB Embedded Wafer Level Ball Grid Array) is a versatile FOWLP technology, providing a robust package platform in a space-efficient design with the very dense interconnection and routing of multiple dies as well as a smaller footprint and lower package profile providing a reliable package solution. Meanwhile, since the utilization of an antenna that is integrated into the packages has been studied as a lowcost solution because the packages can be tested in normal FR4 printed circuit board (PCB) instead of the RF function integrated PCB, the eWLB integrated with molded antenna chip packages (called eWLB antenna in molded package) technology is introduced in this paper. The characterizations for assembly process challenges are evaluated and illustrate the process optimizations of equipment handling, antenna molded chip package fabrication, reconstitution process control and warpage characterization of the molded wafer. In addition, the radio frequency (RF) test validation is performed to verify the performance of scattering parameter (S-parameter), radiation pattern, impedance and detection range of the antenna. In order to prove the reliable quality and yield of the evaluated eWLB antenna in molded packages, package-level reliability tests are studied. Through these results, it will show that this eWLB antenna in molded package integration is a robust and costeffective solution for 77GHz automotive applications.

High-Q Ku-band Microstrip Spiral Resonator in Fan-out Wafer-Level Packaging (FoWLP) Technology for VCO Applications

In this paper, a planar spiral resonator operating at 13 GHz is investigated. The resonator was fabricated using fan-out wafer level packaging (FoWLP) technology. The field analysis highlights the importance of via fence. Two thick film resistors suppress an undesired resonance in proximity of targeted one. The measurements demonstrate a very good correlation in comparison with full-wave simulations. The measured Q-factor defined based on analysis of feedback oscillatory system is about 48. The proposed configuration is suitable for voltage-controlled oscillators (VCOs) with a resonator realized in package.

Gas Permeable Protection Caps for Wafer Level Chip Scale Packaging (WLCSP) of MEMS Environmental Sensors

This work presents new porous environmental protection caps designed for wafer level chip scale packaging (WLCSP) of MEMS environmental sensors. The caps consist of gaspermeable microstructures formed from loose aluminum oxide powder solidified by a ceramic thin film, grown using atomic layer deposition (ALD). For the first time, the full process flow of the proposed approach is demonstrated by manufacture of the cap wafer followed by substrate bonding using glass-frit technology. By analyzing the influence of the caps on the response time of MEMS humidity sensors, this study proves the viability of the proposed packaging technology. In addition, the ability to further functionalize the porous caps is demonstrated by the deposition of a superhydrophobic polymer thin film by chemical vapor deposition.

Optimized Die Preparation and Handling for High Yield Hybrid Die to Wafer Bonding

Hybrid Cu/dielectric bonding is a well-established technology for Wafer-To-Wafer (W2W) bonding, but it is challenging to apply this technology to Die-To-Wafer (D2W) bonding. Very small particles on the die or wafer can lead to voids/non-bonded regions. Processes to clean and activate wafers for hybrid W2W are quite mature, but it is very challenging to apply these to thinned and singulated dies for D2W bonding. To allow a (partial) re-use of the existing wafer level cleaning, metrology and activation processes and equipment, we propose a new concept where dies are being singulated, cleaned and activated on a glass carrier wafer. After the die preparation steps, the dies are directly picked from the carrier wafer. This approach does not involve additional pick & place steps and avoids the use of conventional dicing tapes. The first direct dielectric D2W bonding experiments using this new approach show a very promising bonding yield, with a high number of completely void-free bonded 50 μm thin dies. Additionally, by eliminating dicing tapes, thinned wafers and singulated dies are always supported by a rigid surface, enabling ultrathin die handling. In this study we also report the handling of dies down 10 μm thickness.

Addressing Die Displacement in Lithography Processes for Advanced Packaging Applications

To perpetuate Moore’s Law, semiconductor manufacturers are adopting advanced packaging technology as the mainstream solution. As a result, today, fan-out wafer level packaging is a key enabler of two- and three-dimensional packaging solutions. Among the manufacturing challenges, die displacement in lithography processes has been widely discussed, but a total solution is yet to come. In this study, we demonstrate die-by-die and global wafer alignment strategies available on-board the Kulicke & Soffa LITEQ 500 projection stepper. The versatility of a die-by-die alignment strategy allows for working with reconstituted wafers without resorting to an external metrology tool. The die displacement residuals can be reduced by three orders of magnitude, typically, from 100um to 100nm. The evaluation of overlay accuracy by implementing a die-by-die and global wafer alignment strategy indicates comparable performances. Considering high volume manufacturing, advanced process control of overlay is also capable of applying to a batch of wafers.

Cleaning and Particle Challenges in the Temporary Bonding and Debonding Process

The demands of 5G, Internet of Things and other global technology trends, combined with the increasing cost of scaling down process nodes, have created a shift towards more integrated packaging requirements. The emergence of advanced packaging technologies, such as Fan-Out Wafer Level Packaging (FOWLP), 2.5D/3D IC packaging, and heterogenous integration, brings potential for smaller form factors with increased functionality and bandwidth [1]. Backside processing or thinning of the device wafer is often needed for enabling these technologies. This requires the device wafer be adhered to a rigid carrier wafer using a temporary bonding material (TBM) for mechanical support during handling and processing. Following carrier release, the TBM must be thoroughly removed and cleaned from the device wafer. Many of these adhesives are exposed to high-power lasers or elevated temperatures, making removal more challenging. Sub-micron particle level clean demands for temporary bonding material (TBM) removal are also reaching standards typically reserved for front-end-of-line (FEOL) processing. This is especially crucial in 3D processes such as hybrid bonding where feature and pitch sizes are nearing <1 µm and insufficient cleaning can lead to failures in subsequent bonding processes [2]. Thus, careful consideration of all processing steps is necessary to meet stringent particle demands. This work investigates the removal of coated and baked TBM on silicon wafers, with an emphasis on processing conditions that obtain best particle results. Several chemistries were assessed at the beaker level by performing coupon-level studies and measuring surface properties. Based on these findings, studies with 300-mm wafers were performed using a customizable single-wafer processing tool.

Development of Wafer Level Package Platform for High Reliability Crossover MCUs

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, solder alloys, solder ball pitch and diameter. Developed packages passed and outperformed the following product reliability qualification conditions: high temperature storage life (150°C, 2000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 528 hours), application level temperature cycling ((-40 °C to 125 °C, 600 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

Wafer Level Chip Size Package Integration of an Aero-acoustic MEMS Microphone into a Thin and Flexible Substrate

This publication describes a novel combination of a chip-scale-package-approach for micro-electromechanical systems with flush surface chip embedding in thermal Polyurethane. The concept enables the fabrication of thin and flexible substrates in which sensor chips with fragile membranes are integrated. The presented sensor array can be used for applications like sound source localization in streams of passenger airplanes whilst test-flights.

Goat Performance of Peanut Goat with Supplementation of Feed Wafers Containing Lamtoro Taramba Leaves at Sumbawa Global Farm

Wafer feed is a form of compacted feed to reduce storage space. The ingredients used consist of lamtoro leaves, bran, molasses which are formulated according to the nutritional needs of the feed. This study aims to determine the best level of feed wafers made from lamtoro leaves given to kacang goats. The experimental design used a completely randomized design (CRD) with 3 treatments 4 replicates P1 = 10% feed containing lamtoro leaves, P2 = 12% feed containing lamtoro leaves, P3 = 14% feed containing lamtoro leaves. The results showed that the production performance of kacang goats had a significant effect (P<0.05) on increasing ADG, feed consumption, feed efficiency for kacang goats. It was concluded that the level of giving lamtoro leaf wafers of 12% was the best level

A highly sensitive flexible humidity sensor based on a wafer-level composite material of carbon-quantum-dots@nanofiber clusters

A novel composite material composed of carbon-quantum-dots@nanofiber clusters (CQDs@NFCs) is successfully developed in wafer level, taking it as a sensitive material, a flexible humidity sensor is also developed. Since the composite material is superhydrophilic and contains a super large number of nanopores of different sizes, capillary condensation is able to take place within the composite material at different relative humidity (RH) conditions. Taking advantage of the chemi-physisorption and the capillary condensation, such a sensing material helps to significantly improve sensitivity of the flexible sensor, especially at low RH conditions. Compared with the device adopting only nanofibers as the sensing material, this novel sensor offers a 4.3-time increament in sensitivity within a humidity range of 7%−59% RH, while maintains high sensitivity in the entire humidity range. This heightened sensitivity is crucial for monitoring low-level humidity with high accuracy, making the sensor highly promising for various applications.

Programmable directional color dynamics using plasmonics

Adaptive multicolor filters have emerged as key components for ensuring color accuracy and resolution in outdoor visual devices. However, the current state of this technology is still in its infancy and largely reliant on liquid crystal devices that require high voltage and bulky structural designs. Here, we present a multicolor nanofilter consisting of multilayered ‘active’ plasmonic nanocomposites, wherein metallic nanoparticles are embedded within a conductive polymer nanofilm. These nanocomposites are fabricated with a total thickness below 100 nm using a ‘lithography-free’ method at the wafer level, and they inherently exhibit three prominent optical modes, accompanying scattering phenomena that produce distinct dichroic reflection and transmission colors. Here, a pivotal achievement is that all these colors are electrically manipulated with an applied external voltage of less than 1 V with 3.5 s of switching speed, encompassing the entire visible spectrum. Furthermore, this electrically programmable multicolor function enables the effective and dynamic modulation of the color temperature of white light across the warm-to-cool spectrum (3250 K–6250 K). This transformative capability is exceptionally valuable for enhancing the performance of outdoor optical devices that are independent of factors such as the sun’s elevation and prevailing weather conditions.

Wafer Level Integration of Sub-THz and THz Systems

Wafer Level Integration of Sub-THz and THz Systems

A Low Phase Jitter MEMS Oscillator with Centrally-Anchored Piezoelectric Resonator for Wide Temperature Range Real Time Clock Applications.

This paper describes prototype temperature compensated piezoelectric MEMS oscillators operating in the wide temperature range of -40 °C to 85 °C for RTC applications. The AlN-on-Si resonator is centrally anchored at one point and designed for low power operation with a wide frequency tuning range of 5000 ppm. The oscillators exhibit a stable sinusoidal output at about 497 kHz frequency for time keeping applications with an integrated phase jitter being 10× better than the best commercially available MEMS RTC oscillators for supplementary use in portable devices for clocking audio circuits. The measured oscillator performance remains relatively unchanged when comparing the wafer level packaged capped MEMS resonator with the uncapped one, showing great potential for a high performance low-power RTC oscillator.

Wet chemical poly-Si(n) wrap-around removal for TOPCon solar cells

This work gives an overview on different technological solutions for polysilicon removal in industrial tunnel oxide passivated contact (i-TOPCon) n-type silicon solar cell fabrication. The removal of parasitically deposited poly-Si layers on the front and the edges is a mandatory requirement for a low reverse bias junction leakage current (Irev). A polysilicon removal study on wafer level shows (i) that the efficient removal of the surface oxide layer before poly-Si etching is crucial to achieve short etching times and (ii) that an additive in the KOH solution enhances etching selectivity between poly-Si and silicon oxide surfaces. To evaluate the impact on device level, TOPCon cells have been fabricated in parallel using in-situ n-doped PECVD and LPCVD layers, as well as ex-situ LPCVD poly-Si layers, with another variation of poly-Si removal processes, namely wet chemical inline, wet chemical batch cluster and atmospheric dry etching (ADE). Our results show that a two-minute inline polysilicon removal in hot KOH meets the Irev qualification in case of as deposited in-situ doped layers, whereas for ex-situ doped layers a batch process with a five-minute KOH etching time is needed. LPCVD poly-Si cells show efficiencies above 23%, PECVD poly-Si cells with a batch cluster poly-Si removal process up to 23.4%.