Addressing Die Displacement in Lithography Processes for Advanced Packaging Applications

Abstract

To perpetuate Moore’s Law, semiconductor manufacturers are adopting advanced packaging technology as the mainstream solution. As a result, today, fan-out wafer level packaging is a key enabler of two- and three-dimensional packaging solutions. Among the manufacturing challenges, die displacement in lithography processes has been widely discussed, but a total solution is yet to come. In this study, we demonstrate die-by-die and global wafer alignment strategies available on-board the Kulicke & Soffa LITEQ 500 projection stepper. The versatility of a die-by-die alignment strategy allows for working with reconstituted wafers without resorting to an external metrology tool. The die displacement residuals can be reduced by three orders of magnitude, typically, from 100um to 100nm. The evaluation of overlay accuracy by implementing a die-by-die and global wafer alignment strategy indicates comparable performances. Considering high volume manufacturing, advanced process control of overlay is also capable of applying to a batch of wafers.