Advanced Fan Out Wafer Level Package Development for Small form Factor and High-Performance Microcontroller Applications

Abstract

Over the last few years fan out wafer level packages (FOWLP) have gained significant traction and industry acceptance in product applications that have small form factor requirements. There are different FOWLP flavors that are in high volume production. High density FOWLP that are used for mobile phone application processors have silicon-package integrated process flow with multiple metal layer interconnects. Conventional FOWLP are limited to single or two metal layer interconnects that are used for RF, Wi-Fi, Codec, PMIC, automotive radar applications. In this study a package was evaluated that uses conventional FOWLP process flow with multiple metal layer interconnect for microcontroller (MCU) applications. Extensive front end-back end process Failure Modes and Effects Analysis (FMEA) and optimization were employed to achieve good assembly process quality, manufacturing performance and reliability for the advanced silicon product. The die pre-assembly process of wafer grind, laser groove, and mechanical saw was developed to meet different in line process quality specs related to laser groove depth and profile, no metal debris in scribe line, top side, back side, side wall chipping. Design of Experiment (DOE) legs including different package interconnect layer stack ups, dielectric materials, and solder alloys were evaluated to achieve optimum bill of material combinations that passed JEDEC standards for product reliability qualification. The conditions tested included: Highly Accelerated Test (110°C/85%/3.3V, 528 hours), High Temperature Storage Life (150°C, 2000 hours), Application Level Temperature Cycling ((−40 °C to 125 °C, 600 cycles), Board Level Temp Cycling (−40 °C to 125 °C, 500 cycles) and Board Level Drop Test (1500g/0.5ms, 30 drops). Optimum choice of solder alloy and package redistribution layer stack up led to excellent reliability performance and qualification for all levels of interconnects (silicon-package-board) and successful chip package integration.