Fan-out Wafer Level Packaging Research Articles

High-Accuracy Pick-and-Place of Multiple Dies in Parallel Assisted by Capillary Self-Alignment

Abstract Self-assembly of components driven by liquid surface tension is an attractive complement and even alternative to traditional high-accuracy pick-and-place as it offers high accuracy despite inaccurate robotic part placement. While capillary self-alignment through liquid solder is the standard technology for flip-chip processes, this work presents self-alignment of dies on wetted receptors on a temporary carrier: Low-viscosity liquid is jetted on each receptor where the liquid is contained through generation of hydrophilic and hydrophobic sections on the temporary carrier by plasma treatment. Deterministic die feeding by low-accuracy pick-and-place is conducted for single dies, as well as for batches of three dies and nine dies optimizing the equipment for best throughput to achieve both high accuracy and high productivity. The industry-ready and fully automated chip-to-wafer pick-and-place process is implemented into a fan-out wafer-level packaging production flow proving that self-alignment is capable of easing the stringent requirement for robotic alignment capability for pick-and-place systems in fan-out packaging for the single die-level step in this production chain. The self-alignment process is optimized, and failure modes such as poor liquid confinement, surface contamination, or excess force are identified and eliminated. Post-bond accuracy of <3 μm @ 3 σ at each point of the die is reached for dies of 3.1 mm x 3.1 mm in size. Using parallel die handling, high speeds of around 10 000 units per hour are made possible.

A Hybrid Antenna in Package Solution Using FOWLP Technology

Abstract Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal interconnect losses are introduced by solder bumps. The integration may be unavailable for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on redistributed layers (RDL) is another method for millimeter wave AiP. In this project, a hybrid integration AiP structure is developed. The microwave monolithic integrated circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. Multilayer organic substrate with fine pitch RDL interconnections meets the requirements of wideband antenna design. Modified coplanar waveguide is adopted to feed 2 × 2 aperture array formed on RDL layer. Package warpage is measured using Shadow Moire techniques. The antenna forms an aperture-coupled stacked patch array with bandwidth 25% and gain 8.5dBi for 60 GHz digital communication system. The proposed approach is a convenient hybrid integration solution adopting FOWLP process for millimeter wave AiP systems.

The Redistribution Layer-First Embedded Fan-Out Wafer Level Packaging for 2-D Ultrasonic Transducer Arrays

In this letter, the redistribution layer-first embedded fan-out wafer-level packaging (RDL-first FO-WLP) for 2-D ultrasonic transducer arrays with individual electrical connection is proposed. This process provides the capability of manufacturing thin film circuit with multilayer RDLs and allows signals of elements in arrays being fanned-out to a region larger than the array size. An anisotropic conductive film (ACF) with low curing temperature is employed to provide the electrical and mechanical connection between RDLs and ultrasonic transducer arrays. The thin film circuit with multilayer RDLs and ultrasonic transducer arrays were respectively fabricated and the curing temperature of ACF is close to half of the Curie temperature of the array. This process avoids ultrasonic transducer arrays losing their piezoelectric property, for ultrasonic transducer arrays are not suffering from the high curing temperature of the passivation layers and of the bonding process.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties.

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Electromagnetic Interference Shielding from the Back-Side Metallization of the Chip in Fan-Out Wafer Level Package

Shielding against electromagnetic interference (EMI) is becoming increasingly important as electronics such as wearable devices, sensors, IoT, and smartphones become smaller, faster, and weigh less. Package level EMI shielding has several advantages over board level shielding, such as a higher packaging density and better design flexibility. We developed a new fan-out package structure using back-side under bump metallurgy (UBM) and a substrate (or metal carrier) to improve the thermal characteristics and reduce die shift. UBM and the substrate (or metal carrier), which consisted of highly conductive metals, is effective for EMI shielding. We study EMI shielding effects of UBM and the substrate (or metal carrier). To determine the EMI shielding of the UBM structures, Ti (17 nm thick) and Cu (70 nm thick) were sequentially deposited on a glass substrate using a direct-current (DC) magnetron sputtering system. Then Cu was electroplated or Ni-P was electroless plated with various thicknesses up to 10 µm. Samples were measured under 100 MHz and 1 GHz with 0 dB conditions using a spectra analyzer, which is a near-field measurement equipment. In unpatterened UBM, increase in the Cu or Ni thickness resulted in further enhanced EMI shielding. When the thickness of Cu UBM or Ni-P UBM was bigger than 5 µm or 3 µm, respectively, the UBM exhibited good EMI shielding. A double layer of Cu strips was formed on the back side of the chip to enhance EMI shielding. The larger the overlap between the Cu strip and the upper and lower layers, the better the EMI shielding effect. When this overlap was larger than 0.5 mm, the EMI SE was similar to that of a single unpatterned Cu layer. We demonstrated good EMI shielding in the double-layered structure with a large overlap width between the upper and lower Cu strips, and expect better moisture release in such structures.

Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided.
 
 The impact of different thermo-mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance.
 
 For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full-wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes.
 
 For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within ±1°C.

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging.

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Laue microdiffraction evaluation of bending stress in Au wiring formed on chip-embedded flexible hybrid electronics

Au redistribution layers 10 to 100 μm wide were fabricated on heterogeneously integrated advanced flexible hybrid electronics (FHE) substrates formed by a die-first approach based on fan-out wafer-level packaging. The formed Au metal wiring was meticulously studied for locally induced mechanical stress upon bending (bending radius, BR 20 mm) using Laue microdiffraction (LμD) with synchrotron radiation. It was inferred from the LμD data that upon bending the FHE substrate up to the BR of 20 mm, the Au metal wiring (10 mm long, 100 μm wide, and 500 nm thick) experienced mechanical bending stress amounting to 250 ∼ 300 MPa. The stress values obtained from the LμD studies were close to the stress value of 350 MPa obtained by simulation.

Wafer Level Packaging Technology Applied to Pixel Detectors

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

Low temperature curing polyimides with covalent-boned 5-aminobenzimidazole

Polyimides (PIs) with remarkable mechanical, thermal, dielectric properties have been extensively employed in electronic package of integrated circuit industry. However, PI is imidized at high temperature (>350 °C) traditionally, which limits its application in thin-film transistor and fan-out wafer level package (FOWLP). In this work, active curing catalyst of 5-aminobenzimidazole is introduced in covalent bond to get a low temperature curable polyimide with superior comprehensive properties. The results prove that PI-3 can be imidized completely at 200 °C in 2 h and the imidization index could be as high as 1.03. Besides, the PI films exhibit excellent thermal stability of which the temperature for 5% weight loss is as high as 526 °C and glass transition temperature is 428 °C which is obtained by dynamic mechanical analyzer. Moreover, the tensile test shows the tensile strength of PI-3 is 91 MPa and elongation at break is about 15%. All these results prove the superior performance of the low temperature curing PIs, showing great potentials in the advanced package in the FOWLP and the others.

Solder Joint Reliability Assessment and Pad Size Studies of FO-WLP With Glass Substrate

In recent years, the use of fan-out packaging solutions has boomed in semiconductor-related fields. There are primarily two versions used for mass production: wafer level and panel level. In this research, a glass substrate was used in the design of a fan-out wafer-level package (FO-WLP) and simulations were conducted to predict the reliability of the solder joints. The advantages of glass substrates are their excellent electrical properties, good mechanical rigidity, flatness, and adjustable coefficient of thermal expansion. To verify the robustness of the simulations, a FO-WLP test vehicle was designed, manufactured, and tested under JEDEC thermal cycling condition. In this study, the simulation results were used in an empirical equation to estimate the reliability of the FO-WLP under accelerated thermal-cycling conditions. After simulation validated by experiments, parametric simulations of different design factors can be performed. Using this methodology, we developed a reliable finite element analysis procedure. Thus, structural optimization of the FO-WLP was possible via simulations using various design factors to improve its reliability. The simulation results indicate that a suitable combination of upper, lower pad sizes and the thickness of buffer layer could significantly enhance the reliability life of FO-WLP, and that designers should devote greater attention to these factors to achieve better long-term reliability performance.

Solder joint reliability based on creep strain energy density for SAC305 and doped SAC solders

Parallel to the development of new lead-free solders, electronic packaging has gone through a considerable evolution. A redistribution of layers allows the increase of functionality by increasing the number of inputs/outputsin the packagewhile reducing the size. The reliability of the package is strongly influenced by the reliability of the interconnects. During production and service life, there are thermal processes involved that may lead to thermal fatigue. In this work, a two-dimensional finite elementmodel of a Fan-Out Wafer Level Packaging (FO-WLP) was built, and simulations of thermal test cycles were carried out varying the solder interconnect material: SAC305, SACQ, SACR, orInnoLot. A thermal oscillating load from –40°C to 125°C was applied to the packaging for three hours.State of the art concerning solder joint reliability models based on creep behavior reveals the benefit of using energy-based parameters, as cycles to failure are inversely proportional to the average creep strain energy density.Based on theaverage creep strain energy density simulation results, the reliability of the package withdifferent solderswas compared.The qualitative results suggestthat SACQ has a significant advantage in the operational lifetime compared toSACR, InnoLot, and SAC305.

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling

Abstract An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.

Reliability Simulation of Cu/Polymer interface in Fan-out Wafer Level Packaging

Abstract In order to improve the performance and reliability of the package, the interlayer dielectric (Polymer) must not be delaminated and materials should not fracture due to thermal stresses during the operation or the manufacturing process. If the reliability of the package can be known in advance by simulation, it can be expected to greatly help in material selection and package design. Firstly, we created material-specific master curves (time–temperature superposition) by considering the measurement results of the Peel Test at the Cu/Polymer interface and the mechanical properties of polymer. The critical Energy Release Rate (𝒢𝒸) could be calculated by its master curve. Secondary, we calculated the Energy Release Rate (𝒢) from Finite Element Analysis (FEA) in the package model structure. Finally, delamination is judged by normalizing 𝒢/𝒢𝒸. This study has made it possible to simulate the delamination possibility of Cu/Polymer interface at arbitrary temperatures and displacement rates from basic material data and FEA analysis of the package model structure.

Development of Liquid Molding Compound for Fan-Out Wafer Level Package

FOWLP（ファンアウトウエハレベルパッケージ）にLMC（リキッドモールディングコンパウンド）が広く採用されている中，次世代LMCに要求される微細シリカフィラーを充填したLMCを開発することに成功した。開発されたLMCは平均粒径8 μm程度のフィラーを85 wt%充填し，かつ低温成型を可能にすることによりフィラーの小粒径化と反り特性の両立を達成した。当技術を有したナガセケムテックス製液状成型材料T693/R4000シリーズは，フェイスダウンタイプのファンアウトパッケージに始まり，フェイスアップタイプなど世界中のファンアウトパッケージに使用されている。

Fluorinated graphene/polyimide nanocomposites for advanced electronic packaging applications

AbstractLow dielectric constant and low dissipation factor, superior hydrophobicity, excellent thermal and mechanical property, and good optical performance are desired for advanced electronic packaging of fan‐out wafer level package (FO‐WLP). An effective approach was introduced to fabricate novel fluorinated graphene/polyimide(FG/PI) nanocomposite films in this paper. FG nanosheets exhibit excellent dispersion in the PI matrix due to their high surface area with some oxygen‐containing functional groups, and individual graphitized planar structure. Besides, the effects of the addition of FG on the dielectric, optical, mechanical, thermal properties as well as the hydrophobicity of the films are investigated with controlled amounts of FG. The dielectric constant and loss can be as low as 2.64 (at 106 Hz) and 0.00176 for PI‐0.5wt% FG. And with the increase of the loading of FG, the thermal stability (T5 = 514°C) and mechanical property (tensile modulus = 2.11GPa, tensile strength = 93.23 MPa, elongation at break = 11.60%) has been improved successfully. Besides, the contact angles have been increased from 83° to 92° showing a superior hydrophobicity which is essential for the FO‐WLP. Moreover, the incorporation of FG also proved excellent optical performance of 88% transmittance at 550 nm. Therefore, with the excellent comprehensive performance, the as‐prepared FG/PI films possess widespread applications in the microelectronics especially in FO‐WLP.

Adhesion–delamination phenomena at the interfaces of the dielectric layer

Fan-out wafer-level packaging (FOWLP) has been developed as an enhancement of standard wafer-level packaging solutions and is being intensively researched nowadays. However, issues of delamination remain unsolved. This study focuses on the interfacial characteristics between polyimide (PI) and redistribution layers (RDL) of the FOWLP to decrease the concerns in delamination. The problems of delamination were addressed through simulation and experimentation. In the simulation, the FOWLP package model was established by using the finite element analysis ANSYS software. The results showed various ways to reduce the residual stress, such as by adding a pre-baking process before reflow or by changing the thickness of each PI layer. These ways can effectively reduce the maximum residual stress of the FOWLP and improve the issue of delamination. Moreover, through plasma treatment with the different levels of powers and gases, the adhesion between PI and RDL can improve the overall strengthening of the FOWLP structure. While, in the experimental process, Taguchi design of experiment was utilized to determine the optimal process parameters and key factors. The physical and chemical properties were analyzed, such as the surface roughness via Atomic Force Microscope (AFM) and the surface material compounds by X-ray Photoelectron Spectroscopy (XPS). The relationship between the roughness and delamination was examined.

Significant Die-Shift Reduction and μLED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics

Typical die shift is beyond several tens micrometers or more, which is a serious problem on advanced fan-out wafer-level packaging (FOWLP), to give inevitable misalignment errors in the subsequent photolithography processes for fine-pitch redistributed wiring layer (RDL) formation. In particular, this problem is expected to grow all the more serious in chiplets and tiny dies less than 1 mm in a side. In this work, the use of an anchoring layer is proposed to fix these dies/chiplets on a double-side laminate thermo-release tape and drastically reduce the die shift. In addition, an on-nail photoplethysmogram (PPG) sensor module as a part of flexible hybrid electronics (FHE) is integrated with $\mu $ LED ( $270\,\,\mu \text{m}\,\,\times 270\,\,\mu \text{m}$ ) based on a die-first FOWLP methodology using a biocompatible polydimethylsiloxane (PDMS) mold resin for real-time monitoring pulse wave and percutaneous oxygen saturation (SpO2). The repeated bendability of fan-out Au wirings formed on the PDMS and the current–voltage ( $I$ – $V$ ) behavior of the $\mu $ LED before and after die embedment in the PDMS is characterized.

Reliability Simulation with the Finite Element Analysis (FEA) of Redistribution Layer in Fan-out Wafer Level Packaging

Reliability Simulation with the Finite Element Analysis (FEA) of Redistribution Layer in Fan-out Wafer Level Packaging