Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling

Abstract

Abstract An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.