Wafer Fab Research Articles

Integrate market demand forecast and demand-pull replenishment to improve the inventory management effectiveness of wafer fabrication

The characteristics of the semiconductor industry are short product life cycle, lumpy demand, long lead time, and so on. Theory of constraint suggests a simple replenishment policy to effectively manage supply chain inventory by a demand-pull approach combined with buffer management. However, a demand-pull approach sometimes causes out of stock when the products have lumpy demand. In order to effectively solve this issue, this article integrated market demand forecast information and demand-pull replenishment to improve the inventory management effectiveness of wafer fabrication. An integrated circuit design house provides actual demand per week and market forecast information to the wafer fab. Wafer fab uses inventory buffer to meet customer demand and adjust inventory quantity according to market forecast information and demand-pull replenishment policy. A case of a wafer product that has been drawn from a professional wafer foundry company located in Taiwan is presented to further illustrate the proposed approach. After comparing the result that was obtained from the proposed approach with the traditional demand-pull method, it was found that the proposed approach helps keep high service levels and avoid being out of stock.

Detectability of automotive power MOSFET on-resistance failure at high current induced by Wafer Fab process excursion

This paper presents the meaningful consequence of a minor Wafer Fab process variability, generating on-resistance (RDSon) drift on low voltage vertical power N-MOSFETs dedicated to micro-hybrid automotive application. The research challenge concerned the fact that failure was not detected in production but at customer level; therefore, it was determinant to understand the root cause of this failure mode to drive corrective actions in order to secure customer by detecting and delivering correct parts. The originality of that paper concerns the necessity to use complementary Failure Analysis (FA) investigations, needed to determine the origin of the failure without any possibilities to perform any fault localization. First, assembly investigations are presented to discriminate if the failure was coming from customer or provider. Then, electrical characterizations at high current confirmed the RDSon failure. Thus, strategic physical destructive FA approaches were combined in order to discriminate all potential root causes, using physical step-by-step deprocessing, FIB milling cross-sections and TEM analysis. Finally, a nanometric layer of oxide residue was identified as the origin of the failure and corresponded to a wafer Fab process defect, induced by a lack of oxide overetch at spacer definition process step. These results allowed implementing corrections and improving test screening to protect customer.

All Wet Resist Strip for Improved Semiconductor Process and Product Improvement

Conventionally, plasma ash followed by a wet clean has been used to strip implanted photoresists on all semiconductor technology process flows and nodes. This paper describes the theory and implementation of an All Wet Strip (AWS) process at various post implant levels in the process flow, thus eliminating the need for a plasma treatment. Plasma treatment post implants have shown to add product yield limiting defects most likely eliminated by an All Wet Strip (AWS) process; successfully contributing to cycle time, capacity, cost and yield improvement for semiconductor chips. AWS involves the use of a sulfuric acid and hydrogen peroxide mixture for stripping implanted photo resists, the effectiveness of which has a dependency on the ion implant dose, energy and photo resist type. The paper describes the unique challenges that were overcome to bring the concept from an experimental stage to actual implementation, the process integration plus device sensitivities involved in ramping a process, in a volume 300mm semiconductor wafer fab for complex technologies.

Heuristic scheduling policies for a semiconductor wafer fabrication facility: minimizing variation of cycle times

This paper presents heuristic scheduling policies for semiconductor wafer fabrication facilities. The proposed heuristic scheduling policies include the advanced operation due date (OPNDD) for a sequence control policy and the adaptive constant work-in-process (CONWIP) for an input release control policy. The objective of the proposed scheduling policies is to reduce the variation of cycle times in the wafer fab. The advanced OPNDD sets the higher priority to the front opening unified pod (FOUP) with the smallest operation due date that is computed using a generalized stochastic Petri net model, and at the same time regulates the queue lengths of the FOUPs in each stoker by preventing excessive queue lengths in bottleneck workstations. The adaptive CONWIP controls dynamically the input release time of FOUPs using the adaptive WIP level according to the current status of the wafer fab. The simulation experiments show that the proposed scheduling method is efficient in reducing the variation of cycle times.

A post-classifying fuzzy-neural and data-fusion rule for job scheduling in a wafer fab - a simulation study

This paper proposed a post-classifying fuzzy-neural and data-fusion rule to improve the performance of job scheduling in a wafer fabrication factory (wafer fab). The proposed rule is a hybrid (fusion) of two well-known fluctuation smoothing rules – FSMCT and FSVCT. Several ways of data fusion [including normalised sum (NS), normalised product (NP), condensed normalised product (CNP), weighted normalised product (WNP), and dynamic weighted normalised product (DWNP)] were applied for this purpose. Besides, in order to enhance the scheduling performance of the rule, the post-classifying fuzzy back propagation network (FBPN) approach was applied to improve the forecasting accuracy of the remaining cycle time. To evaluate the effectiveness of the proposed methodology, a production simulation was carried out. According to the experimental results, the proposed methodology outperformed some existing approaches by simultaneously reducing the average cycle time and cycle time variation.

Modelling and analysis of a multi-stage system involving batch processors with incompatible job families

Batch processors can concurrently process more than one job, and are commonly used in complex manufacturing systems such as wafer fabrication facilities (wafer fabs). Previous work has shown that there can be a significant reduction in cycle time when the control of the upstream serial processor is dependent on the batch processor. We wish to determine whether this is also true when the upstream processor is also a batch processor, with smaller capacity. We model a two-stage system with an upstream batch processor and a downstream batch processor under differing simple control policies as a continuous time-discrete state Markov chain. In doing so, we show that the concept of constraining the production of the upstream processor in accordance to the anticipated needs of the downstream batch processor can similarly reduce mean system cycle time when the upstream processor is a smaller batch processor. We also perform simulation experiments, using parameters close to those found in wafer fabs, and confirm that the strategy of prioritising the formation of larger batches for the downstream batch processor typically results in substantial cycle time reductions for the two-stage system.

Designing a Sustainable and Distributed Generation System for Semiconductor Wafer Fabs

Driven by wind and solar photovoltaics technology, the power industry is shifting towards a distributed generation (DG) paradigm. A key challenge in deploying a renewable DG system is the power volatility. This study proposes a visionary energy concept and further presents a mathematical model that could help the large industry consumers adopt this new energy technology. The study seeks to design a grid-connected DG system that is capable of providing the necessary electricity for wafer fabs. Simulation-based optimization algorithm was applied to determine the equipment type and capacity aiming to minimize the DG lifecycle cost. The proposed method was demonstrated on fab facilitates located in three different regions in the US.

Composite Dispatching Rule Design for Photolithography Area Scheduling in Wafer Manufacturing System with Multiple Objectives

This paper investigates the photolithography area scheduling problem in wafer fabrication system, with the objective of simultaneously optimizing multiple performance measures. It has been known that photolithography area is usually the bottleneck work center of a wafer fab, and the scheduling problem in this area plays a significant role in improving the performance of the fab. Most studies of this problem have been focusing on only single objective. Therefore an approach for composite dispatching rule design is proposed to tackle this problem with multiple objectives, and the composite dispatching rule is a linear combination of several elementary dispatching rules with relative weights. Results demonstrate that the composite dispatching rule achieved a great improvement on every objective, compared to the performance of single elementary dispatching rule.

Optimal vehicle allocation for an Automated Materials Handling System using simulation optimisation

The Automated Materials Handling System (AMHS) in the semiconductor industry plays a vital role in reducing wafer cycle times and enhancing fabrication facility (fab) productivity. Due to the complexity of the manufacturing process and the stochasticity introduced by the inherent variability of processing times, the vehicle allocation for the AMHS is a challenging task, especially in 300 mm wafer fabs where the AMHS comprises both the interbay and intrabay systems to perform the timely deliveries. This paper studied the vehicle allocation problem in a typical 300 mm wafer fab. We formulated it as a simulation optimisation problem and proposed a conceptual framework to handle the problem. A discrete event simulation model was developed to characterise the AMHS, and the technique of simulation optimisation was applied to obtain the optimal vehicle allocation for both the interbay and intrabay systems. To demonstrate the feasibility and advantages of the simulation optimisation approach, a photobay example was used to compare the solution derived from the analytical model and simulation optimisation model. Finally, an empirical problem based on real data was conducted to show the viability of the proposed framework in practice.

An integrated scheduling and material-handling approach for complex job shops: a computational study

We suggest an extension of the shifting bottleneck heuristic for complex job shops that takes the operations of automated material-handling systems (AMHS) into account. The heuristic is used within a rolling horizon approach. The job-shop environment contains parallel batching machines, machines with sequence-dependent setup times, and re-entrant process flows. Jobs are transported by an AMHS. Semiconductor wafer fabrication facilities (wafer fabs) are typical examples for manufacturing systems with these characteristics. Our primary performance measure is total weighted tardiness (TWT). The shifting bottleneck heuristic (SBH) uses a disjunctive graph to decompose the overall scheduling problem into scheduling problems for single machine groups and for transport operations. The scheduling algorithms for these scheduling problems are called subproblem solution procedures (SSPs). We consider SSPs based on dispatching rules. In this paper, we are also interested in how much we can gain in terms of TWT if we apply more sophisticated SSPs for scheduling the transport operations. We suggest a Variable Neighbourhood Search (VNS) based SSP for this situation. We conduct simulation experiments in a dynamic job-shop environment in order to assess the performance of the suggested algorithms. The integrated SBH outperforms common dispatching rules in many situations. Using near to optimal SSPs leads to improved results compared with dispatching based SSPs for the transport operations.

Scheduling of multiple in-line steppers for semiconductor wafer fabs

A few prior studies noticed that an in-line stepper (a bottleneck machine in a semiconductor fab) may have a capacity loss while operated in a low-yield scenario. To alleviate such a capacity loss, some meta-heuristic algorithms for scheduling a single in-line stepper were proposed. Yet, in practice, there are multiple in-line steppers to be scheduled in a fab. This article aims to enhance prior algorithms so as to deal with the scheduling for multiple in-line steppers. Compared to prior studies, this research has to additionally consider how to appropriately allocate jobs to various machines. We enhance prior algorithms by developing a chromosome-decoding scheme which can yield a job-allocation decision for any given chromosome (or job sequence). Seven enhanced versions of meta-heuristic algorithms (genetic algorithm, Tabu, GA–Tabu, simulated annealing, M-MMAX, PACO and particle swarm optimisation) were then proposed and tested. Numerical experiments indicate that the GA–Tabu method outperforms the others. In addition, the lower the process yield, the better is the performance of the GA–Tabu algorithm.

Enhancing rule-based scheduling in wafer fabrication facilities by evolutionary algorithms: Review and opportunity

Scheduling is a critical and challenging task in manufacturing systems, especially in large-scale complex systems like wafer fabrication facilities. Although evolutionary algorithms (EAs) have demonstrated many successful applications in the field of manufacturing scheduling, there are very few studies on scheduling of wafer fabs using EAs. Dispatching rules are one of the most common techniques for fab scheduling. In this paper, we present six ways of applying EAs for enhancing the rule-based scheduling system. We provide potential EA-based solutions and review relevant literature. Many of the mentioned viewpoints can serve as new research topics for both researchers in the fields of scheduling and evolutionary computation (EC). Several general EC techniques including multiobjective optimization, expensive optimization, and parallelization are also introduced and shown to be helpful to fab scheduling.

A simulation-based two-stage scheduling methodology for controlling semiconductor wafer fabs

In this paper, we propose an efficient simulation-based two-stage scheduling methodology by integrating vector ordinal optimization (VOO) and response surface methodology (RSM) to make a good scheduling policy for fab operation. The suggested method combines local and global rules into a single rule, with the objective of simultaneously optimizing multiple performance indices. Our approach consists of 2 stages: rule combination selection, and parameter optimization. In the first stage, we apply the VOO techniques to effectively selecting good rule combination. Results show that 1 orders of computation time reduction over traditional simulations can be achieved. In the second stage, we adopt RSM and desirability function to tune the parameters associated to scheduling algorithm. The proposed approach is validated by means of a comparison with other scheduling policies. The results show that the proposed scheduling method is effective.

Rule-based scheduling in wafer fabrication with due date-based objectives

Wafer fabrication is a capital-intensive and highly complex manufacturing process. In the wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers to improve production efficiency and meet customers’ requirements of on-time delivery. In this research we propose a dispatching rule for lot scheduling in wafer fabs, focusing on three due date-based objectives: on-time delivery rate, mean tardiness, and maximum tardiness. Although many dispatching rules have been proposed in the literature, they usually perform well in some objectives and bad in others. Our rule implements good principles in existing rules by means of (1) an urgency function for a single lot, (2) a priority index function considering total urgency of multiple waiting lots, (3) a due date extension procedure for dealing with tardy lots, and (4) a lot filtering procedure for selecting urgent lots. Simulation experiments are conducted using nine data sets of fabs. Six scenarios formed by two levels of load and three levels of due date tightness are tested for each fab. Performance verification of the proposed rule is achieved by comparing with nine benchmark rules. The experimental results show that the proposed rule outperforms the benchmark rules in terms of all concerned objective functions.

3D Glass and Silicon Interposers with TPV vs. 3D ICs with TSV

3D Packaging has been emerging as the dominant theme for more than a decade. It started as package on package stacking in the 1970s for memory devices. More recently, it moved to stacked, wire bonded chips as well as miniaturized package-on-package (POP). Stacking with flip chip soon followed. In all these cases, ICs are fabricated in wafer fabs and packaging of these ICs was subsequently performed independently. The next natural evolution to be expected is to eliminate external interconnections outside the ICs by means of through vias, now called TSVs. But this became revolutionary, complex and costly. It impacted wafer fabrication by virtue of having to co-process transistors, BEOL wiring and TSV interconnections, all in the wafer fab. This is referred to as 3D ICs with TSV. The benefits of 3D ICs are overwhelming. They include highest performance in smallest size by virtue of stacking many ultra-thin ICs and interconnecting them with through-silicon-vias. But such a technology is also complex and costly to manufacture. It presents many other problems that include thermal management, testability, and extendibility. Georgia Tech PRC proposes to demonstrate lower cost and simpler 3D Interposers with TPVs to address most of the above challenges. In this scenario, through-package-vias (TPV) are fabricated in the ultra-thin and low-cost silicon or glass interposers at the same I/O density or pitch as in TSVs in the logic ICs but without the need for TSVs in the logic ICs. Such a concept is 3-dimensional; allowing stacking of ICs on both sides of the interposer with the same I/O pitch as TSVs and yet minimizes the thermal, testability and extendibility problems. This paper presents the status, progress and remaining challenges of 3D Interposer concept at Georgia Tech involving more than 25 companies in a global consortium.

Evaluating the performance of look-ahead policies for upstream serial processor with downstream batch processor serving incompatible job families and finite buffer sizes

Batch processors can concurrently process more than one job. In wafer fabrication, the processing time of a batch is independent of batch size, and only jobs from the same job family can be batched together. We consider a two-stage subsystem of a wafer fabrication facility (wafer fab), comprised of the diffusion furnace (a batch processor) and its upstream serial processor, with random job arrivals. We hypothesise that allowing the serial processor to anticipate the job family preference of the batch processor will reduce the overall cycle time of jobs passing through this system. To evaluate this hypothesis, we model the performance of the two-stage system under different system parameters and processor control policies as discrete state continuous time Markov chains. We characterise the system performance and show that the concept of constraining the production of the upstream processor according to the anticipated needs of the batch processor can reduce the mean cycle time of jobs being processed. We also perform simulation experiments to show that a simple heuristic based on this insight can translate to substantial cycle time reductions for systems with assumptions closer to those found in wafer fabs.

A localised fuzzy-neural fluctuation smoothing rule for job scheduling in a wafer fab

This paper presents a localised fuzzy-neural fluctuation smoothing rule to improve the performance of scheduling jobs in a wafer fabrication factory (wafer fab). The rule is modified from the tailored non-linear fluctuation smoothing (TNFS) rule with some innovative treatments. First, the remaining cycle time of a job is forecasted with an evolving fuzzy-neural approach in order to improve the accuracy. Second, in the original TNFS rule, the adjustable factor is static, and in this rule it becomes dynamic. Third, the adjustable factor in the new rule depends on the jobs gathering before the same machine, and the TNFS rule becomes localised. To assess the effectiveness of the proposed methodology, production simulation is also applied in this study. According to the experimental results, the proposed methodology is better than some existing approaches in reducing the average cycle time and cycle time standard deviation.

Multi-ant colony-based sequencing method for semiconductor wafer fabrication facilities with multi-bottleneck

In this paper, a multi-ant colony optimisation method is proposed to make a sequence plan for a semiconductor wafer fabrication facility (fab) with multi-bottleneck. Its main idea is to find a scheduling solution for each bottleneck of the fab with an ant colony optimisation (ACO) algorithm first, then synchronise these solutions to reunify a sequence plan for these bottlenecks satisfying job sequence constraints, and finally obtain the scheduling plans of non-bottlenecks of the fab subject to that of bottlenecks and job sequence constraints. The sequence plan of the whole fab is translated into the pheromones to guide ant colonies to make their next search processes. There are two kinds of ACO algorithms in the multi-ant colony optimisation method. One (ACO-1) is for common machines and the other (ACO-2) is for batch processing machines. The mini-fab model and a simplified model from a real wafer fab are used to verify and validate the proposed method. The simulation results show that the multi-ant colony optimisation method improves the total weighted tardiness of jobs and the utilities of the bottlenecks with better performances.

Optimising the location of crossovers in conveyor-based automated material handling systems in semiconductor wafer fabs

This research presents several heuristics to optimise the location of crossovers in a conveyor-based automated material handling system (AMHS) for a semiconductor wafer fabrication facility. The objective is to determine the location of crossovers that minimises the total cost of the expected work-in-process on the conveyor and the cost of installing and operating the AMHS with the crossovers. The proposed heuristics are integrated with a queuing-based analytical model incorporating practical hardware considerations of the AMHS, such as turntables and crossovers. To illustrate the proposed heuristics’ practical application they are applied to SEMATECH's virtual wafer fabrication facility. Experimental results demonstrate that under a wide variety of operating conditions and cost scenarios the local improvement heuristic is able to identify the optimal solution and outperform other commonly used heuristics for layout design such as genetic algorithms.

Numerical and experimental investigation on multi-zone chemical mechanical planarization

In this paper, the contact stress distribution on the wafer surface in multi-zone CMP is investigated using finite-element analysis based on a 12-in. and four-zone CMP model. Afterwards, a 12-in. and four-zone polishing head with the same size as the numerical model is developed and CMP experiments are carried out to verify the above numerical calculations. The results show that both the contact stress on the wafer surface and the material removal rate of the wafer can be adjusted by varying the applied load at the zones and the retaining ring in multi-zone CMP, the multi-zone MRR model appears to agree well with the experimental data, and the non-uniformity material removal rate of the wafer can be improved in multi-zone CMP. It is expected that this investigation can give some direct assistance to the 12-in. wafer fab.