3D Glass and Silicon Interposers with TPV vs. 3D ICs with TSV

Abstract

3D Packaging has been emerging as the dominant theme for more than a decade. It started as package on package stacking in the 1970s for memory devices. More recently, it moved to stacked, wire bonded chips as well as miniaturized package-on-package (POP). Stacking with flip chip soon followed. In all these cases, ICs are fabricated in wafer fabs and packaging of these ICs was subsequently performed independently. The next natural evolution to be expected is to eliminate external interconnections outside the ICs by means of through vias, now called TSVs. But this became revolutionary, complex and costly. It impacted wafer fabrication by virtue of having to co-process transistors, BEOL wiring and TSV interconnections, all in the wafer fab. This is referred to as 3D ICs with TSV. The benefits of 3D ICs are overwhelming. They include highest performance in smallest size by virtue of stacking many ultra-thin ICs and interconnecting them with through-silicon-vias. But such a technology is also complex and costly to manufacture. It presents many other problems that include thermal management, testability, and extendibility. Georgia Tech PRC proposes to demonstrate lower cost and simpler 3D Interposers with TPVs to address most of the above challenges. In this scenario, through-package-vias (TPV) are fabricated in the ultra-thin and low-cost silicon or glass interposers at the same I/O density or pitch as in TSVs in the logic ICs but without the need for TSVs in the logic ICs. Such a concept is 3-dimensional; allowing stacking of ICs on both sides of the interposer with the same I/O pitch as TSVs and yet minimizes the thermal, testability and extendibility problems. This paper presents the status, progress and remaining challenges of 3D Interposer concept at Georgia Tech involving more than 25 companies in a global consortium.