Vth Instability Research Articles

Anomalous Threshold Voltage Shift and Surface Passivation of Transparent Indium–Zinc–Oxide Electric-Double-Layer TFTs

Threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) instability and surface passivation effect of transparent indium-zinc-oxide electric-double-layer thin-film transistors (TFTs) are investigated. Unpassivated devices show a large negative threshold voltage shift of 0.68 V in the beginning of light-illuminated negative gate bias stress. Under longer time stress, anomalous positive <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shifts are observed for both unpassivated and passivated TFTs, which is due to the mobile ions drifting in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based solid-electrolyte gate dielectric. After surface passivation, the devices show neglectable negative <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shifts of less than 0.1 V due to the protection of channel against the photodesorption of adsorbed oxygen ions.

P‐32: Improving Reliability of IGZO TFTs via the Front‐channel and Back‐channel Protecting Layers Method

AbstractThe front‐channel protecting layer has been reported to improve GI/IGZO interface and result in undamaged GI surface in coplanar bottom gate IGZO TFTs, and the proposed TFT structures with additional front and back channel protecting showed an effective improvement of Vth shift under both positive and negative gate‐bias stress. The mechanism of Vth shift under the stress has also been studied by this structure. Both front and back channel surfaces are significant. Damage and contamination of these surfaces lead to an increase of Vth instability.

Impact of static and dynamic stress on threshold voltage instability in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors

This letter investigates the impact of static and dynamic stress on threshold voltage (Vth) instability in ultrathin n-channel metal-oxide-semiconductor field-effect transistors with hafnium-based gate stacks. Experimental results indicate Vth shift under dynamic stress is more serious than that under static stress due to charge trapping within the high-k dielectric. Capacitance-voltage techniques demonstrated that electron trapping under dynamic stress was located in the high-k dielectric near the source/drain overlap region rather than throughout the overall dielectric layer. This implies in real circuit operation, the phenomenon of electrons trapped in high-k near the source/drain overlap is the main issue affecting Vth instability.

Interface and bulk effects for bias—light‐illumination instability in amorphous‐In—Ga—Zn—O thin‐film transistors

Abstract— Positive‐current‐bias (PB) instability and negative‐bias—light‐illumination (NBL) instability in amorphous‐In—Ga—Zn—O (a‐IGZO) thin‐film transistors (TFTs) have been examined. The channel‐ thickness dependence indicated that the Vth instability caused by the PB stress is primarily attributed to defects in the bulk a‐IGZO region for unannealed TFTs and to those in the channel—gate‐insulator interface for wet‐annealed TFTs. The interface and bulk defect densities (Dit and Nss, respectively) are Dit = 4.8 × 1011 cm−2/eV and Nss = 7.0×1016 cm−3/eV for the unannealed TFT, which increased to 5.2×1011 cm−2/eV and 9.8×1016 cm−3/eV, respectively, by the PB stress test. These are reduced significantly to Dit = 0.82×1011 cm−2/eV and Nss = 3.2×1016 cm−3/eV for the wet‐annealed TFTs and are unchanged by the PB stress test. It was also found that the photo‐response of a‐IGZO TFTs begins at 2.3 eV of photon excitation, which corresponds to subgap states observed by photoemission spectroscopy. The origin of the NBL instability for the wet‐annealed TFTs is attributed to interface effects and considered to be a trap of holes at the channel‐gate—insulator interface where migration of the holes is enhanced by the electric field formed by the negative gate bias.

Effect of hydrogen in the gate insulator on the bottom gate oxide TFT

The effect of hydrogen in the alumina gate insulator on the bottom gate oxide thin film transistor (TFT) with an InGaZnO film as the active layer was investigated. TFT with more H‐containing alumina films (TFT A) fabricated via atomic layer deposition using a water precursor showed higher stability under positive and negative bias stresses than that with less H‐containing alumina deposited using ozone (TFT B). While TFT A was affected by the pre‐vacuum annealing of GI, which resulted in Vth instability under NBS, TFT B did not show a difference after the pre‐vacuum annealing of GI. All the TFTs showed negative‐bias‐enhanced photo instability.

Low-Frequency Noise 측정을 통한 Bottom-Gated ZnO TFT의 문턱전압 불안정성 연구

Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (△Vth) than those with thickness of 40 nm. However the △Vth is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level(SID/ID 2 ) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the Vth instability under electrical stress.

Improvement in the photon-induced bias stability of Al–Sn–Zn–In–O thin film transistors by adopting AlOx passivation layer

This study examined the impact of the passivation layer on the light-enhanced bias instability of Al–Sn–Zn–In–O (AT–ZIO) thin film transistors. The suitably passivated device exhibited only a threshold voltage (Vth) shift of 0.72 V under light-illuminated negative-thermal stress conditions, whereas the device without a passivation layer suffered from a huge negative Vth shift of &amp;gt;11.5 V under identical conditions. The photocreated hole trapping model could not itself explain this behavior. Instead, the light-enhanced Vth instability of the unpassivated device would result mainly from the photodesorption of adsorbed oxygen ions after exposing the AT–ZIO back-surface in an ambient atmosphere.

The influence of the gate dielectrics on threshold voltage instability in amorphous indium-gallium-zinc oxide thin film transistors

We investigated the threshold voltage (Vth) instability for various gate dielectrics (SiNx and SiOx) in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs). The a-IGZO TFTs with SiNx 150 °C exhibited reasonable electrical performance (field-effect mobility of 8.1 cm2/V s and Ion/off ratio of &amp;gt;108) but showed huge Vth shift under positive gate bias. The TFTs with SiOx dielectrics exhibit smaller Vth instability than those of SiNx dielectrics. This behavior can be explained by using simple charge trapping into the gate insulators and the difference of Vth instability on various dielectrics may be originated from the hydrogen contents, providing high density of charge traps in gate dielectrics.

Charge-transition levels of oxygen vacancy as the origin of device instability in HfO2 gate stacks through quasiparticle energy calculations

We perform quasiparticle energy calculations to study the charge-transition levels of oxygen vacancy (VO) in HfO2. The negative-U property of VO can explain flat band voltage shifts and threshold voltage (Vth) instability in hafnium based devices. In p+ Si gate electrode, the Fermi level pinning varies by up to 0.55 eV, in good agreement with the measured values. Depending on gate bias, VO traps electrons or holes from the Si channel, causing the Vth instability. It is suggested that short time-scale charge trapping/detrapping is due to metastable VO−1 centers, whereas stable VO−2 centers dominate long time-scale instability.

Investigation of Bias-Temperature Instability in work-function-tuned high-k/metal-gate stacks

The impact of Vth-adjusting layers on high-k/metal-gate n- and pFinFET Vth stability is investigated. Additional insight is gained by monitoring ΔVth recovery transients over several decades in time. Vth-adjusting capping layers deposited directly on top of the gate dielectric degrade the Vth stability. The Vth stability improves as the capping layers are buried in the gate metal and are thus isolated from the gate dielectric. A combination of a capping layer thickness and depth in the metal gate is found that practically eliminates nFET Vth instability.

Origin of threshold voltage instability in indium-gallium-zinc oxide thin film transistors

We investigated the impact of the passivation layer on the stability of indium-gallium-zinc oxide (IGZO) thin film transistors. While the device without any passivation layer showed a huge threshold voltage (Vth) shift under positive gate voltage stress, the suitably passivated device did not exhibit any Vth shift. The charge trapping model, which has been believed to be a plausible mechanism, cannot by itself explain this behavior. Instead, the Vth instability was attributed to the interaction between the exposed IGZO backsurface and oxygen and/or water in the ambient atmosphere during the gate voltage stress.

Threshold voltage instability of p-channel metal-oxide-semiconductor field effect transistors with hafnium based dielectrics

Threshold voltage Vth instability is one major issue for future metal-oxide-semiconductor field effect transistors (MOSFETs) with hafnium (Hf) based gate dielectrics. Previous attention was focused on n-channel MOSFETs (nMOSFETs) and the implicit assumption is that it is not important for p-channel MOSFETs (pMOSFETs). This work shows that the Vth instability of pMOSEFTs can be higher than that of nMOSFETs for a sub-2nm nitrided Hf layer. Unlike nMOSFETs, the Vth instability of pMOSFETs is insensitive to measurement time, does not saturate as stress voltage increases, and is not controlled by carrier fluency. Using Hf silicates is less effective in suppressing it. Some speculations are given on the defect and physical processes responsible for the instability.

Impact of nitrogen in HfON gate dielectric with metal gate on electrical characteristics, with particular attention to threshold voltage instability

The impact of nitrogen (N) in HfON gate dielectric on electrical characteristics, particularly on charge trapping induced threshold voltage (Vth) instability, has been investigated in n-channel metal-oxide-semiconductor field effect transistor with TaN metal gate. Compared to HfO2, the enhanced gate capacitance, slightly increased gate leakage current, and degraded interface properties were observed in the HfON gate dielectric. The incorporation of N into HfO2 also caused mobility degradation at low effective field region. Moreover, charge trapping induced Vth instability was found to be severer in HfON than in HfO2, which could be attributed to increased bulk traps induced by the incorporated N.

A Comparative Study of $\hbox{HfTaON/SiO}_{2}$ and $\hbox{HfON/SiO}_{2}$ Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO2 gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO2 interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO2 gate stack provided much lower gate leakage current against SiO2 , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO2, improved thermal stability was also observed in the HfTaON/SiO2 gate stack. Moreover, charge-trapping-induced threshold voltage V th instability was examined for the HfTaON/SiO2 and HfON/SiO2 gate stacks. The HfTaON/SiO2 gate stack exhibited significant suppression of the Vth instability compared to the HfON/SiO2, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO2 gate stack indicate that it has the potential to replace conventional SiO2 or SiON as gate dielectric for advanced CMOS applications

Fast $V_{\rm th}$ Instability in $\hbox{HfO}_{2}$ Gate Dielectric MOSFETs and Its Impact on Digital Circuits

Fast component of Vth instability in MOSFET with HfO 2 gate dielectric is systematically measured and characterized. A charge-trapping/detrapping model is used to simulate the Vth instability with overall agreement with the experiments. Experimental and modeling data provide and predict the fast Vth shift under both static and dynamic stress conditions. These data are incorporated into HSpice circuit simulation to evaluate the impact of Vth shift on the performance of digital circuit in realistic situations. Considering the properties of the fast Vth instability, circuit performance can be optimized by circuit design in addition to process improvements. This should be included to the guideline of process development and circuit design for future CMOSFET digital systems

Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique

Threshold voltage (VTH) instability in metal oxide semiconductor field transistors (MOSFETs) with high dielectric constant (k) gate dielectrics has been investigated with an inversion pulse measurement technique, which can detect fast dielectric charging/discharging within microseconds (μs). The results indicate that VTH instability can be significantly underestimated by conventional VTH measurement techniques. Based on temperature-dependent stress data, it is suggested that charging and discharging are determined by direct tunneling and thermally assisted processes, respectively.

Trapping/De-Trapping Gate Bias Dependence of Hf-Silicate Dielectrics with Poly and TiN Gate Electrode

Constant voltage stress induced Vth shift and its detrapping characteristics under the negative gate bias has been extensively investigated with HF-silicate dielectrics with poly and TiN gate electrode. The threshold voltage shift in negative-channel metal-oxide semiconductor (NMOS) transistors under the positive gate bias stress is found to be associated mostly with the reversible electron trapping. A proper negative bias can be used to de-trap the electrons accumulated during the positive stress. However, an aggressive de-trapping can cause an additional Vth instability due to the excessive de-trapping of existing charge or additional hole trapping at the interface with poly gate. TiN metal gate is found to be more stable with de-trapping negative gate bias. To de-trap the electrons accumulated in the dielectric during the positive constant voltage stress (CVS), the negative bias and its duration should be chosen very carefully to avoid the additional charging associated with the hole trapping.