Trapping/De-Trapping Gate Bias Dependence of Hf-Silicate Dielectrics with Poly and TiN Gate Electrode

Abstract

Constant voltage stress induced Vth shift and its detrapping characteristics under the negative gate bias has been extensively investigated with HF-silicate dielectrics with poly and TiN gate electrode. The threshold voltage shift in negative-channel metal-oxide semiconductor (NMOS) transistors under the positive gate bias stress is found to be associated mostly with the reversible electron trapping. A proper negative bias can be used to de-trap the electrons accumulated during the positive stress. However, an aggressive de-trapping can cause an additional Vth instability due to the excessive de-trapping of existing charge or additional hole trapping at the interface with poly gate. TiN metal gate is found to be more stable with de-trapping negative gate bias. To de-trap the electrons accumulated in the dielectric during the positive constant voltage stress (CVS), the negative bias and its duration should be chosen very carefully to avoid the additional charging associated with the hole trapping.