Voter Circuit Research Articles

Fault Identification in Modified Hybrid Digital Pulse Width Modulation using Triple Modular Redundancy

In this paper, the fault analysis is performed for the identification in the Modified Hybrid Digital Pulse Width Modulation by making use of the Triple Modular Redundancy method. The developed algorithm is real time implemented using the Xilinx Artix 7 FPGA device. The Modified Hybrid Digital Pulse Width Modulation is designed for the purpose of minimizing the Turn-ON and Turn-OFF delays in the triggering event of the generated Digital Pulse Width Modulation. Though additional compensatory circuits are added for the delay reduction, the area utilization is still low when implemented in FPGA device. Also, the Triple Modular Redundancy consists of three times of MHDPWM signal generation to check for the fault occurrence. For the sake of validating the fault identification, the majority voter circuit is used that could find the error at the earliest. The proposed method is checked for errors by inducing within the VHDL code and trailed with multiple duty cycle values. The proposed fault identification method is validated for VLSI parameters such as area, delay and power.

Single Point Failure Free Interleaved Synchronous Buck Converter for Microsatellite Electrolysis Propulsion

This article describes the design and implementation of a dc–dc converter used to power a microsatellite on-board electrolyzer. The proposed topology is a four-phase interleaved synchronous buck converter with output current control. The proposed converter is single point failure free (SPFF), so in case of any individual component failure, the functionality of the system is not compromised. SPFF operation is achieved using individual protections in each buck phase, redundant output current control, and redundant clock systems. Besides, analog majority voter circuits are used to select the correct control signal after any failure and to isolate it. Detailed mathematical analysis and circuit design are presented. Furthermore, a 40-W prototype has been implemented to validate the concept. Experimental results presented show the correct performance of the system in every case and its fault tolerant capability. In addition, the ac behavior and stability of the system have been studied and verified under the full range of possible operating conditions. Finally, efficiency measurements are presented.

Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction

A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naïve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL’s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only naïve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction.

FPGA based Design of Triple Modular Redundancy for Hybrid Digital Pulse Width Modulation Generator

This paper proposes the Triple Modular Redundancy checker for the Hybrid Digital Pulse Width Modulation generator to verify the correctness in the output signal. The proposed design involves replicating the Hybrid Digital Pulse Width Modulation Generator thrice and the majority voter circuit validates the correct output by considering the two accurate signals out of the three outputs. The digital pulse width modulation generator is broadly classified as Counter-based Digital Pulse Width Modulation, Delay line-based Digital Pulse Width Modulation, and Hybrid-based Digital Pulse Width Modulation. Among the three methods, the Hybrid based Digital Pulse Width Modulation is preferred as the Counter-based Digital Pulse Width Modulation uses high clocking frequency and the Delay line-based Digital Pulse Width Modulation occupies a large area. The proposed Triple Modular Redundancy is implemented using the FPGA and parameters such as power analysis and device utilization chart.

Hybrid and Double Modular Redundancy (DMR)-Based Fault-Tolerant Carry Look-Ahead Adder Design

The adder is an essential component of data paths, and as a result of the shrinking size of electronic devices, it is becoming more susceptible to manufacturing defects and soft errors. Thus, the design of fault-tolerant adders is crucial to the correct operation of arithmetic circuits. In this paper, we propose different fault-tolerant carry look-ahead adder designs against single-bit soft errors based on double modular redundancy DMR and hybrid fault-tolerant schemes. In DMR-based design, we combine a partial hardware redundancy scheme with a protected C-element to achieve full soft error masking, while in the hybrid design, we employ a partial hardware redundancy combined with a parity prediction scheme to improve fault tolerance capability of the adder while reducing area overhead. We use two different voter circuits for merging the partial hardware redundancy into the carry generation logic and to achieve higher fault masking rate and lower area overhead in comparison with existing approaches. Simulation results show that the proposed design schemes take precedence over other schemes in terms of failure rate, area overhead and delay overhead.

NMR configurations with novel majority voter circuits to mask multiple module faults

Mission, safety, and business-critical applications need uninterrupted operation with correct results. But due to the technology shrinking, the microelectronic circuits can be affected by many faults like permanent, transient, and intermittent. So, there is a considerable demand for designing fault-tolerant systems. Hardware redundancy configurations have been widely used to protect or mask faults. In this research article, to mask multiple faults, N-modular redundancy (NMR) configurations are deployed, namely 5-MR and 7-MR configurations, which are implemented to mask two and three function module errors. Two majority voter (MV) circuits with 5-MR and 7-MR have been proposed, respectively. Simulation results are obtained with Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). With ASIC, 120 nm technology is used with BSIM4 Spice simulation parameters. Also, the majority voters are evaluated with a band-pass filter as the function module on Altera DE2-115 FPGA using the Quartus II synthesis tool. The very high-speed integrated circuits hardware description language is used with FPGA implementation. Simulation results reveal that the proposed MV circuits obtain better results than the existing methods.

A Novel Scheme for Fault Tolerant Computing

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic

Conventional CMOS-based logic circuits are approaching their limits when it comes to speed and energy consumption, so the development of new electronic components becomes critical. Memristor is a nano-structured special electronic device with the advantages of simple structure, low power consumption and easy integration. This invention supplys a new method for developing complex logic circuits. This article mainly presents the design of a five-person voter circuit. The OR/AND logic can be accomplished by varying the polarity of two parallel memristors. On the basis of the two logic circuits, adder and comparator are constructed. Further, based on the adder and comparator, a five-person voter is implemented. The correctness and rationality of the five-person voter based on MRL are confirmed via logistical analysis and simulation. Compared with the traditional logic circuits, the logic circuit designed in this paper has advantages in area cost. The realization of the five-person voter circuit further proves that the logic circuit based on memristor can be cascaded. The research results are expected to build more complex circuits, which may provide a reference for the design of other practical circuits.

Eight-Person Voter Implementation Based on Hewlett-Packard Memristor

The logic function based on memristor has been proved and can be applied to the future large scale integrated circuits. In this paper, we use logic circuit based on memristor to realize the function of eight-person voter. The basic logic circuit designed in this paper is consisted of two Hewlett-Packard memristors in series connection and an operational amplifier. Operational amplifiers are used to regulate the output voltages to meet the requirements of the input signals in the next stage circuits. The adder, binary comparator and multi-input logic gate are realized by using the designed logic circuit. Full adders, binary comparators and multi-input logic gates are combined into eight-person voter circuit. Theoretical analysis and spice simulation results verify the feasibility of the circuit under different cases. This method is expected to be applied to more complex voter logic circuits based on memristor.

Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs

As a consequence of the technology scaling, the reduced amount of energy needed to store information impacts the Linear Energy Transfer Threshold (LETth), implying in circuits more sensitive to radiation faults. Hardware redundancy techniques such as the Triple Modular Redundancy are constantly used to mitigate this problem. However, the weakness of the redundancy technique is the voter circuit, and for this reason, alternative designs have been proposed in the literature to improve the robustness of this block. This work investigates the robustness of different majority voter topologies in the presence of Single Event Transient (SET). A layout-level analysis using stick diagrams is fulfilled to analyze the impact a SET causes in diffusion areas shared by transistors, and a fault masking ratio is used to measure the voter robustness. Then an electrical-level analysis was done based on the information provided from the previous study to investigate the threshold LET. The results obtained in this study shown that the topologies can endure a LET up to 1.86 MeV·cm−2/mg considering the 32 nm CMOS technology.

Optimized Voter Circuit for Fault Tolerant Implementation in TMR

Due to scaling down of devices, circuits are vulnerable to manufacturing faults, radiation interference and various other faults. This may result in malfunctioning of circuits due to the occurrence of such faults. So performance, reliability, power and area have now become even more critical factors to look into. Due to degradation of components over time and noise in general, the overall design may be affected and produce incorrect results. Hence, fault tolerant design is now very critical in electronics circuit design. In space applications, Single Event Upsets (SEU) can occur, which can lead to system failure. To mitigate such errors, TMR (Triple Modular Redundancy) technique can be used. Simulations and analysis were performed on Cadence Virtuoso ADE and RTL compiler. In this paper, we present our fault tolerant voter circuit which might tolerate a fault and provide error free output by masking the fault which may occur in any one of the three modules. The proposed voter circuit takes 24 transistors compared to 26 for conventional voter circuit. Results also show 50% percent reduction in falling delay. The proposed voter circuit, using transmission gates takes 14 transistors and power consumption is also significantly reduced.

Triple transistor based triple modular redundancy with embedded voter circuit

This paper presents a new static redundancy technique that combines the redundancy at transistor level with redundancy at functional level and offers a very good reliability at minimal increase in the hardware, delay and power overheads. The proposed method does not require any external voter hardware as in triple modular redundancy (TMR) method; instead the last level gates of the triplicated modules of the circuit are combined and designed using fault tolerant triple transistor logic which act as an embedded voter circuit. This method offers higher reliability at lesser area and shorter critical path compared to the most popular TMR method as well as other recently proposed static fault tolerant methods. This makes our design suitable for designing fault tolerant systems for real-time resource constrained applications. We have provided theoretical analysis as well as simulation results proving the superiority of our method.

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

CMOS based circuits are more susceptible to the radiation environment as the critical charge (Qcrit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 µA.

RASP-TMR: An Automatic and Fast Synthesizable Verilog Code Generator Tool for the Implementation and Evaluation of TMR Approach

Triple Modular Redundancy (TMR) technique is one of the most well-known techniques for error masking and Single Event Effects (SEE) protection for the FPGA designs. These FPGA designs are mostly expressed in hardware descrip-tion languages, such as Verilog and VHDL. The TMR technique involves triplication of the design module and adding the majority voter circuit for each output port. Building this triplication scheme is a non-trivial task and requires a lot of time and effort to alter the code of the design. In this paper, the RASP-TMR tool is developed and presented that has functionalities to take a synthesizable Verilog design file as an input, parse the design and triplicate it. The tool also generates a top-level module in which all three modules are instantiated and finally adds the proposed majority voter circuit. This tool, with its graphical user interface, is implemented in MATLAB. The tool is simple, fast and user-friendly. The tool generates the synthesizable design that facilitates the user to evaluate and verify the TMR design for FPGA-based systems. A simulation scenario is created using Xilinx ISE tools and ISim simulator. Different fault models are examined during simulations such as bit-flip and stuck at 1/0. The results using various benchmark designs demonstrate that the tool produces synthesizable code and the proposed majority voter logic perfectly masks the error/failure.

A Fault Tolerant Voter Circuit for Triple Modular Redundant System

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an application-specific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8×8 array multiplier, bitwise XOR operation and a 3 × 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared.

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters

Majority voters are typically used in redundancy hardening techniques aiming to increase the reliability of nanoscale circuits. Besides, Spin Transfer Torque Magnetic Tunnel Junction (STT-MJT) has been identified as the most promising candidate for low power and high speed applications. In this paper, we present two majority voter circuits based on nanometer STT-MTJ. By using STMicroelectronics FDSOI 28nm process and a precise STT-MTJ compact model, electrical simulations have been carried out to compare their performances and analyze their reliability. Both radiation sensitivity and variability have been investigated in the reliability-aware analysis.

Modified Ternary Karnaugh Map and Logic Synthesis in Ternary Quantum Dot Cellular Automata

ABSTRACTModified Karnaugh map for ternary logic synthesis and logic circuit realization in ternary quantum dot cellular automata (tQCA) is presented in this research article. This modified mapping technique is used for the realization of ternary proposition logic and greater minimization in ternary logic synthesis in tQCA. The comparison is made with earlier proposed ternary mapping technique for logic minimization. The tQCA logic circuit design is also described. The tQCA layout of diverse logic gates like ternary majority voter (TMV), ternary inverter (T_INV), and ternary wire (T_WIRE) circuit is explored. In case study, 3:1 tQCA multiplexer design and tQCA layout is presented.

Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )

This study presents the design and implementation of an efficient structure for fault tolerant bit-parallel polynomial basis multiplication and squaring over GF(2 m ), based on a similar strategy of Roving method with a minimum overhead. The Roving method is an efficient method for the circuits in which many similar and independent structures exist. The architectures of the polynomial basis multiplication and squaring over binary finite fields have inherent regularity in their subsections of the structures. Therefore, they are compatible to the applied version of Roving fault tolerant method. To generalise the proposed architecture, the multiplication and squaring operations are examined for different primitive polynomial, including general irreducible polynomials, irreducible pentanomials and irreducible trinomials. In the proposed design, the extracted common circuit has low hardware utilisation compared with that of the main circuit. The fault tolerant circuit is constructed by using three copies of the common circuit, a comparator and a voter circuit. The comparator and voter have parallel architectures with low critical path delays, which is a critical factor in any highly computational system. The design has been successfully verified and synthesised onVirtex-4 XC4VLX200 FPGA using Xilinx ISE 11. The results show an overall improvement in the speed and hardware usage compared with those of previous designs.