Abstract
CMOS based circuits are more susceptible to the radiation environment as the critical charge (Qcrit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 µA.
Highlights
The reliability issues are a major concern in semiconductor ICs designed for medical, space and defense applications that operate in a high radiation environment
At deep sub-micron technology, the CMOS integrated circuits are more likely to experience the occurrence of Single Event Transient (SET) and Multiple Event Transients (METs)
This paper proposed Fully Robust Triple Modular Redundancy (FRTMR) latch with novel majority voter circuit in 45 nm technology which can tolerate single and multi-node upsets
Summary
The reliability issues are a major concern in semiconductor ICs designed for medical, space and defense applications that operate in a high radiation environment. If the transient fault occurs on the drain terminal of NMOS transistor, a negative current spike is generated [22]. If the transient fault occurs on the drain terminal of PMOS transistor, positive current spike is generated. The output node recovers by removal of the current source [2]–[4] If this transient pulse is propagated through memory element the Single Event Upset (SEU) occurs. The majority voter circuit designed with less number of transistors and less sensitive nodes compared to the existing classical TMR latch used in [12]. FRTMR consumes considerably low power and less area than the existing classical TMR latch because of the less number of transistors used in majority voter circuit.
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