Design Of Voltage Regulator Research Articles

Analysis and Design of Low Noise Voltage Regulator With Integrated Single BJT Bandgap Reference Upto 10 mA Loads

Analysis and Design of Low Noise Voltage Regulator With Integrated Single BJT Bandgap Reference Upto 10 mA Loads

Design of Step Voltage Regulator Based on IGBT

The introduction of distributed generation (DG) into distribution systems is expanding due to carbon neutral policies. DG with intermittent output characteristics brings frequent voltage variations in distribution systems. Generally, a step voltage regulator (SVR) is installed in the long distribution line and controls its voltage, which has limits of stable voltage regulations due to the slow tap-changing rate, switching losses, and short life span. To solve those problems, this paper proposes an IGBT-based SVR using zero-voltage switching. It is verified that the stable operation can be obtained through simulation by PSCAD/EMTDC 4.6 software and empirical experiments.

A 1.8 V, 10 mA low dropout voltage regulator for IoT application in 90 nm CMOS technology

A complementary metal-oxide-semiconductor CMOS low dropout voltage regulator (LDO) design flow using 90 nm CMOS technology is described and simulated in this paper. The circuit consists of an analogue LDO with using PMOS pass device, an error amplifier, a bandgap voltage, a biasing circuit, a feedback resistive network sized to have the desired closed loop gain. This LDO was designed to maintain stable voltage at 1.8 V and 10 mA of current output in low resistive load. The LDO regulator achieves 105 uA quiescent current, -47 PSRR@13 KHz noise frequency. The final design occupies approximately 0.05 mm<sup>2</sup>. The results were satisfying and make the designed circuit suitable for IoT application.

Low-Dropout Voltage Regulator Designed with Nanowire TFET with Different Source Composition Experimental Data

This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and nanowire MOSFET. The devices are mod-eled using lookup tables implemented with experimental measures of TFETs with different source compositions (Si, SiGe and Ge) and MOSFET. In order to compare the designs, the transistors of the differential amplifier in all LDOs is biased with gm/ID = 8 V-1 with a load of 1 μA and 10-pF. It is shown that all TFET based LDOs are stables without the need of a compensator capacitor (CC) even for higher load capacitance. For the MOSFET LDO, a CC of 5-pF capacitor was used. The study shows that the TFET based LDOs deliver higher effi-ciency due to the possibility to operate with low bias current. In the transient analysis it is shown that the TFET LDOs have lower overshoot but higher delay. The Ge-TFET LDO pre-sented settling times for load and line transient close to the MOSFET LDO with 15 μs and 30 μs. The SiGe-TFET LDO shows the best loop gain (60 dB), while the Si-TFET LDO deliv-ers lowest quiescent current (300 pA) and the Ge-TFET have the best GBW (70 KHz) and PSR (-52 dB). It is concluded that the TFET based LDOs can deliver specifications similar or bet-ter than the MOSFET LDO even without the need of CC and with less power consumption.

Improve the performance of automatic voltage regulator for power system using self-tuning fuzzy-PID controller

The optimal design of the automatic voltage regulators for a synchronous machine are positively reflected on the quality of voltage stability. This paper is concerned with the design of an AVR by adopting three control techniques. The first one was designed according to the traditional proportional integration-derived (PID) controller while the fuzzy logic was adopted in design the second powerful controller, finally the fuzzy PID controller for an automatic voltage regulator (AVR) based on fuzzy logic technology, selftuning fuzzy proportional integration-derived (STFPID) have been designed to tuning the gains of the PID controller (KP, KI and KD). To confirm the efficiency of the proposed control systems, a simulation was carried out, and the results showed that the designed STFPID controller achieves the best performance of the AVR system, and gives the preferable tracking low rise time, lower overshoot, least stetting time, minimal steady state error, and gives the ideal response against PID and fuzzy logic technology.

Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.

Design and preliminary results of a shunt voltage regulator for a HV-CMOS sensor in a 150 nm process

This paper presents the design and preliminary results of a shunt voltage regulator and two different bandgap reference designs for use with a monolithic High Voltage CMOS (HV-CMOS) sensor in a 150 nm technology node. One bandgap reference design is based on Bipolar Junction Transistors (BJTs) as the reference element of the circuit — the rest of the circuit is entirely designed with Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs). The second bandgap reference design makes use of MOSFETs exclusively.

Coupled Inductors With an Adaptive Coupling Coefficient for Multiphase Voltage Regulators

As modern microprocessors continuously advance, a high-efficiency, high-power-density voltage regulator design with fast transient response is a must. Compared with the non-coupled-inductor-based solution, a multiphase buck converter with an indirect-coupled inductor (ICL) can dramatically improve the circuit transient response without increasing the inductor current ripple and sacrificing efficiency. However, a design conflict between the steady-state performance and transient response exists for the conventional ICL structure with a given inductor size. This article first analyzes the benefits and limitations of the conventional ICL based on a detailed modeling process. Then, an adaptive-coupled inductor structure is proposed to solve the issue. This is realized by applying a variable inductor in the extra winding loop of an ICL. By self-adjusting the coupling coefficient, the proposed structure can further improve the circuit transient response without increasing the phase inductor current ripple. A four-phase buck converter with the proposed inductor structure is experimentally tested, and it shows that a 25.6% output voltage overshoot reduction or a 21.8% output capacitance reduction can be realized by the proposed coupled inductor structure.

Novel Combined Load Frequency Control and Automatic Voltage Regulation of a 100% Sustainable Energy Interconnected Microgrids

Frequency and voltage deviations are two main problems in microgrids, especially with the increase in the penetration level of renewable energies. This paper presents novel techniques to apply combined the load frequency control and automatic voltage regulation of two interconnected microgrids. The two microgrids are operated by solar energy and bioenergy technologies and include energy-storage facilities. The control is applied using a novel accelerating PID controller (PIDA), which is compared to state-of-the-art control schemes. The controllers are designed using a new doctor and patient optimization technique (DPO), which is compared to state-of-the-art techniques. The combined design of load frequency controllers and automatic voltage regulators is also compared to a standalone design. The comparisons are carried out by testing the system performance at each operation condition in addition to indicators such as integral absolute error for frequency and voltage and integral time absolute error for frequency and voltage. The results show that a combined DPO–PIDA design of LFC–AVR schemes for fully sustainable microgrids has better performance than other standalone designs and other control and optimization alternatives.

Design and simulation of low dropout voltage regulator using 180nm technology

Low Dropout (LDO) Voltage Regulators are the linear regulators which drives upon a very small differential voltage. The main components of the Low dropout voltage regulators are Error amplifier, Pass device, voltage reference source and Voltage divider network. The low dropout voltage regulator uses a variable input to give a steady, constantly controlled, low-noise DC output voltage. This is a linear voltage regulator that includes a small voltage drop among the input as well as the output that works even when the output voltage is extremely close to the input voltage. The Error amplifier circuit which is one of the components in Low dropout voltage regulator is designed in the standard 180nm CMOS technology, with supply voltage of 1.6V, the gain of the error amplifier is 74db, Band-gap reference circuit is implemented to produce stable reference voltage which is independent of temperature variations. The bandgap reference voltage circuit gives the output voltage of 1.2V. The low dropout voltage regulator produces constant output voltage of 1.8V for the input voltage range 2.1V to 3.5V and it provides constant output voltage for load variations.

Design and Construction of an Automatic Voltage Regulator for a Synchronous Alternator

Abstract The Automatic Voltage Regulator (AVR) is necessary to keep the terminal voltage of a loaded alternator constant. It is widely used to increase the regulation and stability of synchronous alternators especially in bulk power plants where efficiency and stability is of paramount importance. The AVR is a feedback controller that varies the excitation of the alternator to support a constant output voltage by increasing or decreasing the excitation level of the alternator as the load varies. In this research, the transfer functions of the various stages of the AVR are decided for the purpose of the design of the Voltage Regulator. The performance of the AVR is decided by the basic no load and load test on the alternator. The results show that there was tremendous improvement in the terminal voltage of the alternator with the AVR and a significant drop in the terminal voltage of the alternator without the AVR.

Design of an AC Voltage Regulator Using a Harmonic Free TCR

In this work, a T-connected phase voltage-controlling scheme is presented. The mid branch of the T-configuration is a pure susceptance controlled smoothly in inductive and capacitive operating modes. This susceptance is built of a TCR shunted by a filtering circuit, which is designed to suppress the three significant odd harmonics released by the TCR. The left hand branch is a pure inductive impedance, while the right hand one is a pure capacitive impedance equal in magnitude to the left hand one. If the input phase voltage is below its rated value VLrated, then the controlling susceptance is capacitive and its value is set such that it can raise the load voltage to its desired rated value. If the input voltage is above its rated value, then the susceptance is inductive causing the load voltage reduce to its desired rated value. The regulator is harmonic free and capable of keeping its output voltage within its rated value even though its input voltage is varying in the range of (0.75-1.25)VLrated. Once a voltage disturbance occurs, the regulator approaches its steady state response within five cycles of the input phase voltage. The regulator is capable of supplying 220 V, 50 Hz, 3 kVA loads.

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

This paper presents the design of an output-capacitorless low-dropout voltage regulator (OCL-LDO) capable of driving a wide range of load capacitance and supplying a wide range of load current while maintaining excellent load and line regulations, thanks to the combined indirect-direct nested Miller compensation which ensures stability and maintains a high loop gain over the whole range of load condition. Fabricated in a 0.18-μm CMOS process and consuming 14 μA of quiescent current, the OCL-LDO, while supplying the load current between 0 mA to 100 mA, is capable of driving the load capacitance in the range of 0-1 nF; with a minimum load current of 1 mA, however, the OCL-LDO can drive up to 10 nF of load capacitance. Over such wide load-current and load-capacitance ranges, the OCL-LDO achieves DC load and line regulations of 0.025 mV/mA and 0.5 mV/V, respectively.

Optimal design of Fractional order PID controller based Automatic voltage regulator system using gradient-based optimization algorithm

Considering the superior control characteristics and increased tuning flexibility of the Fractional-Order Proportional Integral Derivative (FOPID) controller than the conventional PID regulator, this article attempts to explore its application in the optimal design of the Automatic Voltage Regulator (AVR). Since FOPID has two additional tuning parameters (µ and ʎ) than its mentioned conventional counterpart, its tuning process is comparatively difficult. To overcome the stated issue, a self-regulated off-line optimal tuning method based on the Gradient-Based Optimization (GBO) algorithm is adopted in the current study. The optimal FOPID gains are obtained by minimizing the selected Fitness Function (FF) that is chosen as Integral Time Absolute Error (ITAE) in the current study. The simulations are performed using MATLAB/SIMULINK 2018a to test and compare the performance of the proposed GBO-based optimal AVR design based on the dynamic response, stability, and robustness evaluation metrics with some of the recently published metaheuristic optimization algorithm based optimal AVR designs in the literature. The results show that the proposed AVR design provides the most optimal dynamic response and enhanced stability among the considered AVR designs, thus proves its efficacy and essence.

Design and Simulation of a Capless Low Drop Out Voltage Regulator

Portable electronic devices mostly used battery as their primary source for operation hence longer running batteries or Power resources or vital for any portable device need for stable voltage supplies have led to the development of low dropout voltage regulators low dropout regulators provide stable regulated output voltage in various operating conditions which makes it useful in portable devices that design of high performance and stable low dropout voltage regulator is a challenge nowadays with decreasing device size and increasing power densities. The proposed circuit used a 5pack architecture of error amplifier. This paper proposes the study of behavior of the LDO voltage regulator with internal capacitors i.e., capless. The regulated voltage of 1.8V is obtained using the typical power supply of 2.2V obtained dropout voltage of 400mv with the delay of 12.77micro sec, power consumed 1.816W. The proposed design produced DC gain of 31.77db,with the load current variation of 0 to 20mA. The capless LDO architecture is verified in the Cadence 180nm technology. The architecture provides a stable gain and plot for both Temperature and Load Variations. The stability issues are overcome using the compensation techniques which uses a current amplifier and a capacitor in the differentiator configuration. The current amplifier implemented uses current mirror with current copying ratio of unity.

Supercapacitor-Assisted Techniques and Supercapacitor-Assisted Loss Management Concept: New Design Approaches to Change the Roadmap of Power Conversion Systems

All electrical and electronic devices require access to a suitable energy source. In a portable electronic product, such as a cell phone, an energy storage unit drives a complex array of power conversion stages to generate multiple DC voltage rails required. To optimize the overall end-to-end efficiency, these internal power conversions should waste minimal energy and deliver more to the electronic modules. Capacitors are one of the main component families used in electronics, to store and deliver electric charges. Supercapacitors, so called because they provide over a million-fold increase in capacitance relative to a traditional capacitor of the same volume, are enabling a paradigm shift in the design of power electronic converter circuits. Here we show that supercapacitors could function as a lossless voltage-dropping element in the power conversion stages, thereby significantly increasing the power conversion stage efficiency. This approach has numerous secondary benefits: it improves continuity of the supply, suppresses voltage surges, allows the voltage regulation to be electromagnetically silent, and simplifies the design of voltage regulators. The use of supercapacitors allows the development of a novel loss-circumvention theory with applicability to a wide range of supercapacitor-assisted (SCA) techniques. These include low-dropout regulators, transient surge absorbers, LED lighting for DC microgrids, and rapid energy transfer for water heating.

The Frequency- and the Time-Domain Design of a Dual Active Bridge Converter Output Voltage Regulator Based on the D-Decomposition Technique

Commonly used variants of the proportional-integral, PI, and the integral-proportional, IP, compensator gains selections, merged with the $\mathfrak {D}$ -decomposition technique are presented in this paper. The motivation to this work is the willingness to check whether such a combination can lead to unified and perhaps simplified approach in this matter. Therefore, the $\mathfrak {D}$ -decomposition technique has been effectively combined with the frequency- and the time-domain driven requirements regarding the control dynamics. Criteria such as the gain- and phase-margins, $(GM, PM)$ , the sensitivity, $M_{\text {S}}$ , the pole placements by means of the $(\sigma, \omega _{\text {d}})$ and the $(\xi, \omega _{\text {n}})$ , and the overshoot with the rise time $(\delta, t_{\text {r}})$ are considered. It has been shown that the control design effort can be reduced by the means of the $\mathfrak {D}$ -decomposition to intuitive judgments in the proportional and integral gains coordinates $(K_{\text {P}}, K_{\text {I}})$ with parametric curves. As such it can be thought of as a promising scenario in a case considered. The analyses are presented and discussed in details. They are conducted basing on example of output voltage closed loop control of the Dual Active Bridge, DAB, converter. The circuit operates under the phase shift control scheme. The control-to-output transfer function identification and the control circuit delays are included in the analyses. The case analysis have shown that the time domain requirements are less effectively met with the PI regulator when compared to its IP configuration. This is due to the commonly used simplifications during conversion between the $(\xi, \omega _{\text {n}})$ and the $(\delta, t_{\text {r}})$ in presence of uncompensated zero of the closed loop transfer function. The paper contains complete and intelligible approach to dedicated mathematical investigations verified experimentally.

Optimal design of robust resilient automatic voltage regulators

Uncertainties in the plant model parameters and perturbations in the controller gains imposed by implementation errors represent a challenge to ensure robust stability and controller non-fragility simultaneously. Optimal design of robust non-fragile proportional–integral–derivative (PID) controller is presented for an automatic voltage regulator (AVR). The PID design relies basically on Kharitonov theorem and optimization by future search algorithm (FSA). The proposed algorithm has low computational complexity and fast convergence rate because it utilizes both local and global search methods. Further, FSA can improve the exploration characteristic and prevent trapping in local optima by updating its random initial. The PID controller is optimized by FSA to cope with expected parametric uncertainties of the plant model and tolerate its gain perturbations such that robust stability and controller non-fragility are simultaneously met. An interval plant model is suggested to account for model uncertainties where only eight extreme plants derived by Kharitonov theorem are considered in design. FSA-based PID optimization is constrained by the stability conditions of Kharitonov’s plants derived using Routh–Hurwitz. A new figure-of-demerit (FoD) based performance index is suggested to enforce simultaneous minimization of the time domain specifications. The suggested objective function is represented by a weighted sum of FoD of nominal response and the sum of reciprocals of the perturbation radii of PID gains. The output results of the recommended design are compared to that of artificial bee colony (ABC) algorithm and teaching–learning based optimization (TLBO) algorithm, multi-objective extremal optimization (MOEO), and non-dominated sorting genetic algorithm II (NSGA II). The results can confirm better response of the suggested technique measured up to other techniques where robustness and non-fragility are simultaneously ensured.

Design of an Automatic Voltage Regulator Using MATLAB for Real-Time ECG Signal Transmission Monitoring applications

Design of an Automatic Voltage Regulator Using MATLAB for Real-Time ECG Signal Transmission Monitoring applications