Design and Simulation of a Capless Low Drop Out Voltage Regulator

Abstract

Portable electronic devices mostly used battery as their primary source for operation hence longer running batteries or Power resources or vital for any portable device need for stable voltage supplies have led to the development of low dropout voltage regulators low dropout regulators provide stable regulated output voltage in various operating conditions which makes it useful in portable devices that design of high performance and stable low dropout voltage regulator is a challenge nowadays with decreasing device size and increasing power densities. The proposed circuit used a 5pack architecture of error amplifier. This paper proposes the study of behavior of the LDO voltage regulator with internal capacitors i.e., capless. The regulated voltage of 1.8V is obtained using the typical power supply of 2.2V obtained dropout voltage of 400mv with the delay of 12.77micro sec, power consumed 1.816W. The proposed design produced DC gain of 31.77db,with the load current variation of 0 to 20mA. The capless LDO architecture is verified in the Cadence 180nm technology. The architecture provides a stable gain and plot for both Temperature and Load Variations. The stability issues are overcome using the compensation techniques which uses a current amplifier and a capacitor in the differentiator configuration. The current amplifier implemented uses current mirror with current copying ratio of unity.