Voltage Margin Research Articles

Si CMOS Image-Sensors Designed With Hydrogen-Ion Implantation Induced Nanocavities for Enhancing Output Voltage Sensing Margin via Proximity Gettering

Si CMOS image-sensor (CIS) cells were designed by implementing proximity relaxation gettering sites of hydrogen-ion implantation-induced nanocavities (20–35 nm in diameter) underneath Si photodiode regions to enhance the sensing margin of output voltage in CIS cells. They enabled almost no degradation in the output voltage sensing margin, although ~ $ 10^{{\mathsf {14}}}$ cm $^{{\mathsf {-2}}}$ of Fe, Cu, Ni, and Co contaminants were introduced in the photodiode regions of CIS cells, demonstrating an excellent relaxation gettering ability. However, Si CIS cells designed with p/p++ epitaxial wafers, which are widely used, showed that the sensing margin of the CIS cells significantly decreased as the concentration of Cu and Ni contaminants in the Si photodiode regions increased, indicating no segregation gettering ability.

An Enhanced DC Voltage Droop-Control for the VSC--HVDC Grid

This paper introduces an enhanced droop-based dc-voltage control method, including dead-band, for applications to the high-voltage direct-current (HVDC) grid that utilizes the voltage-sourced converter (VSC) technology. The proposed droop-control structure also autonomously imposes energy balance between the HVDC grid and its host ac system. The droop-control method (1) divides the VSC stations into four groups, (2) activates the droop-control of each group based on a prespecified voltage margin, and (3) introduces an improved power-voltage characteristic for desirable VSC station dynamic performance. Feasibility and performance of the proposed control method are evaluated based on time-domain simulation studies in the PSCAD platform, using the IEEE-39-Bus system that imbeds a five-terminal VSC–HVDC grid. Each VSC station is a monopolar modular multilevel converter (MMC). The study results show that the proposed droop-control method enables the HVDC-AC system to reach a new steady state after transient events.

Unaprijeđeno upravljanje momentom visokobrzinskog pogona s asinkronim motorom bez mjerenja brzine

This paper presents improved torque control scheme for a high speed sensorless induction motor drive. The proposed high speed torque control scheme substitutes the flux oriented control by the voltage angle control in the flux weakening regime. This scheme uses maximum of available inverter voltage, alleviates well known problems of current control schemes in conditions with insufficient voltage margin and avoids the influence of estimated speed error to the achieved flux level. The algorithm uses similar slip control as flux oriented control algorithm, but is applied without an outer flux trajectory reference which is typical for the flux weakening, providing a fast and well damped torque response even if error in estimated speed is present. Experiments confirm the effectiveness of proposed torque control algorithm, smooth transition from the flux oriented control in the base speed region to the voltage angle control in the flux weakening, superior dynamic performance of the voltage angle torque control, and its robustness to an estimated rotor speed error.

Industrial 100-MVA EAF Voltage Flicker Mitigation Using VSC-Based STATCOM With Improved Performance

As an industry consumer of electric power, an electric arc furnace (EAF) is a major voltage flicker source that causes significant power-quality (PQ) problems. The fast response of the static synchronous compensator (STATCOM) makes it an efficient solution for improving PQ in distribution systems facing this kind of very nonlinear load. In this study, for voltage flicker mitigation of a 100-MVA EAF installed in Europe, a voltage-source-converter (VSC)-based STATCOM with high bandwidth is designed. The STATCOM's current reference includes both active and reactive current components. The performance of the STATCOM in voltage flicker mitigation is highly improved by applying this control strategy which uses the dc voltage margin of the VSC to provide for an active compensating current without oversizing the STATCOM converters capacitor. In this paper, first, the proposed STATCOM is studied through a generalized steady-state analysis. Second, the STATCOM's control strategies for voltage flicker mitigation are introduced and simulation results are provided and compared. Finally the complete model is validated by field tests over a 60-MVAr industrial STATCOM. Static and dynamic performance of the STATCOM is evaluated and voltage fluctuation mitigation studies are performed and discussed. The voltage flicker mitigation is evaluated through onsite measurements respecting international standards.

Design and analysis of optimised class E power amplifier using shunt capacitance in the output structure

ABSTRACTIn this paper, a class E power amplifier (PA) with operating frequency of 1 MHz is presented. MOSFET non-linear drain-to-source parasitic capacitance, linear external capacitance at drain-to-source port and linear shunt capacitance in the output structure are considered in design theory. One degree of freedom is added to the design of class E PA, by assuming the shunt capacitance in the output structure in the analysis. With this added design degree of freedom it is possible to achieve desired values for several parameters, such as output voltage, load resistance and operating frequency, while both zero voltage and zero derivative switching (ZVS and ZDS) conditions are satisfied. In the conventional class E PA, high value of peak switch voltage results in limitations for the design of amplifier, while in the presented structure desired specifications could be achieved with the safe margin of peak switch voltage. The results show that higher operating frequency and output voltage can also be achieved, compared to the conventional structure. PSpice software is used in order to simulate the designed circuit. The presented class E PA is designed, fabricated and measured. The measured results are in good agreement with simulation and theory results.

Experimental stand-alone self-excited induction generator driven by a diesel motor

This paper presents an experimental work to design and size a diesel generator (DG). The basic system is equipped with a 1.5kW self-excited induction generator (SEIG), a diesel motor (DM), a static voltage compensator (SVC) and controllers. A proportional integral controller is used to meet the requirement of the SEIG frequency regulation. A controlled voltage source is performed by using an SVC with a fuzzy controller, which adjusts voltage by varying the amount of the injected reactive power. An experimental set-up is used to identify the SEIG parameters and select the convenient bank of capacitors that minimize the SEIG starting up time and fix the convenient margin of voltage. The system has been tested by simulation using models implemented by Matlab/Simulink software. The simulation results confirm the efficiency of the proposed strategy of voltage regulation.

(Invited) Analysis of Traps in 3-D NAND Flash Memory Cells

Recently, demand for non-volatile memory have increased since digital applications using non-volatile memory (NVM) have rapidly increased in market. To satisfy this market demand, minimum feature size in NAND flash memory was scaled down to 1x nm technology node. Because of reducing cell size, there are some problems such as increased process cost, poor reliability characteristics, and narrowing threshold voltage (V th) window and margin. However, the demand for increasing cell density is continuously requested in NVM device market. As a result, 3-D NAND flash memory structure has been considered as a device structure to increase memory capacity and reduce bit cost in NAND flash memory technology. As a structure advantageous for mass production, word-line stacked structures using charge trap flash (CTF) memory structure and poly-Si body have emerged by industry. The structure is suitable for high-density, but yet it has many reliability problems. There are two main issues. One is high trap density caused by adapting poly-Si body and high-k dielectric. The interface (between the body and the tunneling oxide) and poly-Si body have many traps due to grain boundary, and the traps affect device characteristics and reliability. Also, defects in high-k dielectric cause unwanted electron trapping/detrapping. The other issue is trapped charge distribution caused by adapting CTF structure because the charge trap layer is continuous between adjacent cells. Moreover, trap density (N t) profile of charge trap layer affects program and erase speeds, V th window, retention characteristics. Thus, suppressing charge distribution in the charge trap layer and characterizing N t profile of the charge trap layer are very important in 3-D NAND flash memory. In this presentation, the behavior of transient bit-line current (I BL) is firstly characterized during reading after giving a pre-bias (V pre) to two different cells in 3-D NAND flash memory having poly-Si body. Depending on the dominance of charge trapping in high-k blocking dielectric or the interface between the tunneling oxide and the poly-Si body, transient I BL shows different behaviors. The capture and emission of charges in two trap sites are systematically analyzed by investigating transient I BL behaviors during reading with various V pres and fast & pulsed I-Vs. Second, to understand the influence of the lateral charge distribution at charge trap layer, V ths over retention time are measured with three modes of adjacent cell states at different temperatures (T). It is found that the programmed adjacent cells give better retention characteristic by suppressing the lateral charge redistribution during retention time. The accurate N t profiles of the charge trap layer in 3-D NAND flash memory can be extracted by considering the lateral charge redistribution and utilizing derived retention model. Moreover, N t profile of deep energy level is also extracted by using AC-transconductance (g m) dispersion with frequency (f). During measuring AC-g m characteristic of a cell, channel carriers interact with traps in the gate stack by applying a small signal to the control gate and the number change of channel carriers interacting with the small signal makes the f dispersion of AC-g m. With measuring retention property and AC-g m dispersions of cells, the N t profile in a wide energy range can be extracted. Third, the interface trap density (D it) in a wide range of subgap energy is extracted from the cells of 3-D NAND flash memory by performing conductance measurements. By performing the measurement at various temperatures (T), accurate D it profile which includes a trap profile having Gaussian function near the midgap energy can be obtained.

Selector Requirements for 3D Resistive Switching Crossbar Array Based on Writing Margin Evaluation

The decreasing writing voltage margin of a selected cell in low resistance state with respect to the increasing series resistance to the cell, in association with the sneak currents in 3D crossbar RRAM, is examined. The validity of the analysis based on the proposed model was confirmed by comparing its results with those from a SPICE simulation when full voltage scheme (Vdd scheme), appropriate for RRAM with any type of selector, is considered. A 1diode-1resistive switching memory (1D1R) with extremely high rectification ratio of ~109 was fabricated, and its performances were analyzed according to the proposed model. As a result, plausible designing strategy for further scaling of the 3D crossbar RRAM is provided. In order to switch a selected cell (yellow cell) from LRS to HRS, word line voltage larger than the writing voltage of a selected cell is required owing to the presence of series resistances of the selected w- and b-lines. The main idea for this study is that the series resistance is not only attributable to the wire resistances of selected w- and b- lines but also the additional resistance by the sneak currents. As the sneak currents, determined by the array size (NxN) and the selectivity (s) of the selection device, intensifies the voltage drop on the selected word and bit lines, even larger word line voltage is needed with the increasing sneak currents effect.. At the same time, the word line voltage is also applied to the non-selected neighboring cells comprising sneak current paths. Among the unselected cells, a cell with the smallest/largest series wire resistance of the selected word and bit line becomes the most/least disturbed one. The HSPICE simulated results confirm the proposed model except for the certain range of parameters, whose plausibility is not guaranteed even with the reading margin evaluation. Typical RRAM devices with rectifying selector and the reference values according to the recent reports are organized. According to the operation criteria in the writing margin points of view, only the device with the operation voltage at the reverse bias being smaller than the writing voltage at the forward bias is applicable to the actual array integration. Such writing margin evaluation is demonstrated based on the experimental parameters of a 1D1R RRAM. It was found that confirming the writing margin of a RRAM device may propose an even tougher requirement while designing the device, compared to its reading margin, so this aspect needs higher attention. In conclusion, the operation criteria for high density crossbar RRAM based on the writing margin analysis include a large operation voltage even in the reverse bias to withstand the disturbance during the writing of a selected cell, a high selector performance, and small wire resistances of w- and b- lines. Improved from the conventional understanding, where only wire resistances of w- and b-lines are considered during writing, the proposed model includes the sneak currents even in the writing operation providing an even more comprehensive method of evaluating a RRAM device performance within the crossbar array picture than that of only the selectivity based read margin analysis.

An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies

Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization.

Performance of two modified optimization techniques for power system voltage stability problems

The development of optimization techniques in power system is to determine the sizing of Flexible AC Transmission System (FACTS) devices such as Unified Power Flow Series Compensator (UPFC) controller in improving the voltage stability and bus voltage margin. An attempt is made to modify the Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) with Hybrid-Genetic Algorithm (H-GA) for determination of sizing of the device. Fast Voltage Stability Index (FVSI) is used to identify the location of the device to be connected. The proposed methods are implemented in IEEE 30 Bus system and its results are tabulated for each technique.

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of $\sim 10$ dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

NAND flash memory’s reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose–Chaudhuri–Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive VRef shift (AVS) and VTH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (VRef) based on temperature, W/E cycles and retention-time. AVS stores the optimal VRef’s in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between VTH states. DVO reduces BER by 80%.

Dynamic Behaviour of Multi-Terminal VSC-Based HVDC after a Converter Outage: DC Control Strategy

aim of this paper is to evaluate the effect of DC-voltage control strategy on the dynamic behaviour of multi-terminal Voltage-Source Converter (VSC)-Based HVDC after a converter outage. In this paper, two dc voltage control strategies are considered: (i) standard voltage margin method (SVMM) and (ii) standard voltage-droop method (SVDM). The impact is evaluated in this paper using time-domain simulations on a simple test system using DIgSILENT ® PowerFactory TM considering a sudden disconnection of a converter-station. Simulation results demonstrate how important is the dc-voltage control strategy and the location/number of dc-buses involved in the dc-voltage on the dynamic response of the MTDC systems. The voltage margin control is capable of surviving a converter outage just if this converter is operating in constant power mode.

Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits.

PMMA-HfO<sub>x</sub> 유-무기 하이브리드 저항변화 메모리 제작

In this study, we developed the solution-processed PMMA-<TEX>$HfO_x$</TEX> hybrid ReRAM devices to overcome the respective drawbacks of organic and inorganic materials. The performances of PMMA-<TEX>$HfO_x$</TEX> hybrid ReRAM were compared to those of PMMA- and <TEX>$HfO_x$</TEX>-based ReRAMs. Bipolar resistive switching behavior was observed from these ReRAMs. The PMMA-<TEX>$HfO_x$</TEX> hybrid ReRAMs showed a larger operation voltage margin and memory window than PMMA-based and <TEX>$HfO_x$</TEX>-based ReRAMs. The reliability and electrical instability of ReRAMs were remarkably improved by blending the <TEX>$HfO_x$</TEX> into PMMA. An Ohmic conduction path was commonly generated in the LRS (low resistance state). In HRS (high resistance state), the PMMA-based ReRAM showed SCLC (space charge limited conduction). the PMMA-<TEX>$HfO_x$</TEX> hybrid ReRAM and <TEX>$HfO_x$</TEX>-based ReRAM revealed the Pool-Frenkel conduction. As a result of flexibility test, serious defects were generated in <TEX>$HfO_x$</TEX> film deposited on PI (polyimide) substrate. On the other hand, the PMMA and PMMA-<TEX>$HfO_x$</TEX> films showed an excellent flexibility without defect generation.

An amorphous titanium dioxide metal insulator metal selector device for resistive random access memory crossbar arrays with tunable voltage margin

Resistive random access memory (ReRAM) crossbar arrays have become one of the most promising candidates for next-generation non volatile memories. To become a mature technology, the sneak path current issue must be solved without compromising all the advantages that crossbars offer in terms of electrical performances and fabrication complexity. Here, we present a highly integrable access device based on nickel and sub-stoichiometric amorphous titanium dioxide (TiO2−x), in a metal insulator metal crossbar structure. The high voltage margin of 3 V, amongst the highest reported for monolayer selector devices, and the good current density of 104 A/cm2 make it suitable to sustain ReRAM read and write operations, effectively tackling sneak currents in crossbars without compromising fabrication complexity in a 1 Selector 1 Resistor (1S1R) architecture. Furthermore, the voltage margin is found to be tunable by an annealing step without affecting the device's characteristics.

4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors

A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0- $\mu\mbox{m} \mbox{Nb}/\mbox{AlO}_{x}/\mbox{Nb}$ nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of $3.09 \times 1.66 \mbox{mm}^2$ . It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of $6.25 \times 10^9$ 32-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any $4n$ -bit processing.

Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of 64 x 64, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of 128 x 128, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.