(Invited) Analysis of Traps in 3-D NAND Flash Memory Cells

Abstract

Recently, demand for non-volatile memory have increased since digital applications using non-volatile memory (NVM) have rapidly increased in market. To satisfy this market demand, minimum feature size in NAND flash memory was scaled down to 1x nm technology node. Because of reducing cell size, there are some problems such as increased process cost, poor reliability characteristics, and narrowing threshold voltage (V th) window and margin. However, the demand for increasing cell density is continuously requested in NVM device market. As a result, 3-D NAND flash memory structure has been considered as a device structure to increase memory capacity and reduce bit cost in NAND flash memory technology. As a structure advantageous for mass production, word-line stacked structures using charge trap flash (CTF) memory structure and poly-Si body have emerged by industry. The structure is suitable for high-density, but yet it has many reliability problems. There are two main issues. One is high trap density caused by adapting poly-Si body and high-k dielectric. The interface (between the body and the tunneling oxide) and poly-Si body have many traps due to grain boundary, and the traps affect device characteristics and reliability. Also, defects in high-k dielectric cause unwanted electron trapping/detrapping. The other issue is trapped charge distribution caused by adapting CTF structure because the charge trap layer is continuous between adjacent cells. Moreover, trap density (N t) profile of charge trap layer affects program and erase speeds, V th window, retention characteristics. Thus, suppressing charge distribution in the charge trap layer and characterizing N t profile of the charge trap layer are very important in 3-D NAND flash memory. In this presentation, the behavior of transient bit-line current (I BL) is firstly characterized during reading after giving a pre-bias (V pre) to two different cells in 3-D NAND flash memory having poly-Si body. Depending on the dominance of charge trapping in high-k blocking dielectric or the interface between the tunneling oxide and the poly-Si body, transient I BL shows different behaviors. The capture and emission of charges in two trap sites are systematically analyzed by investigating transient I BL behaviors during reading with various V pres and fast & pulsed I-Vs. Second, to understand the influence of the lateral charge distribution at charge trap layer, V ths over retention time are measured with three modes of adjacent cell states at different temperatures (T). It is found that the programmed adjacent cells give better retention characteristic by suppressing the lateral charge redistribution during retention time. The accurate N t profiles of the charge trap layer in 3-D NAND flash memory can be extracted by considering the lateral charge redistribution and utilizing derived retention model. Moreover, N t profile of deep energy level is also extracted by using AC-transconductance (g m) dispersion with frequency (f). During measuring AC-g m characteristic of a cell, channel carriers interact with traps in the gate stack by applying a small signal to the control gate and the number change of channel carriers interacting with the small signal makes the f dispersion of AC-g m. With measuring retention property and AC-g m dispersions of cells, the N t profile in a wide energy range can be extracted. Third, the interface trap density (D it) in a wide range of subgap energy is extracted from the cells of 3-D NAND flash memory by performing conductance measurements. By performing the measurement at various temperatures (T), accurate D it profile which includes a trap profile having Gaussian function near the midgap energy can be obtained.