Abstract
Si CMOS image-sensor (CIS) cells were designed by implementing proximity relaxation gettering sites of hydrogen-ion implantation-induced nanocavities (20–35 nm in diameter) underneath Si photodiode regions to enhance the sensing margin of output voltage in CIS cells. They enabled almost no degradation in the output voltage sensing margin, although ~ $ 10^{{\mathsf {14}}}$ cm $^{{\mathsf {-2}}}$ of Fe, Cu, Ni, and Co contaminants were introduced in the photodiode regions of CIS cells, demonstrating an excellent relaxation gettering ability. However, Si CIS cells designed with p/p++ epitaxial wafers, which are widely used, showed that the sensing margin of the CIS cells significantly decreased as the concentration of Cu and Ni contaminants in the Si photodiode regions increased, indicating no segregation gettering ability.
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