Selector Requirements for 3D Resistive Switching Crossbar Array Based on Writing Margin Evaluation

Abstract

The decreasing writing voltage margin of a selected cell in low resistance state with respect to the increasing series resistance to the cell, in association with the sneak currents in 3D crossbar RRAM, is examined. The validity of the analysis based on the proposed model was confirmed by comparing its results with those from a SPICE simulation when full voltage scheme (Vdd scheme), appropriate for RRAM with any type of selector, is considered. A 1diode-1resistive switching memory (1D1R) with extremely high rectification ratio of ~109 was fabricated, and its performances were analyzed according to the proposed model. As a result, plausible designing strategy for further scaling of the 3D crossbar RRAM is provided. In order to switch a selected cell (yellow cell) from LRS to HRS, word line voltage larger than the writing voltage of a selected cell is required owing to the presence of series resistances of the selected w- and b-lines. The main idea for this study is that the series resistance is not only attributable to the wire resistances of selected w- and b- lines but also the additional resistance by the sneak currents. As the sneak currents, determined by the array size (NxN) and the selectivity (s) of the selection device, intensifies the voltage drop on the selected word and bit lines, even larger word line voltage is needed with the increasing sneak currents effect.. At the same time, the word line voltage is also applied to the non-selected neighboring cells comprising sneak current paths. Among the unselected cells, a cell with the smallest/largest series wire resistance of the selected word and bit line becomes the most/least disturbed one. The HSPICE simulated results confirm the proposed model except for the certain range of parameters, whose plausibility is not guaranteed even with the reading margin evaluation. Typical RRAM devices with rectifying selector and the reference values according to the recent reports are organized. According to the operation criteria in the writing margin points of view, only the device with the operation voltage at the reverse bias being smaller than the writing voltage at the forward bias is applicable to the actual array integration. Such writing margin evaluation is demonstrated based on the experimental parameters of a 1D1R RRAM. It was found that confirming the writing margin of a RRAM device may propose an even tougher requirement while designing the device, compared to its reading margin, so this aspect needs higher attention. In conclusion, the operation criteria for high density crossbar RRAM based on the writing margin analysis include a large operation voltage even in the reverse bias to withstand the disturbance during the writing of a selected cell, a high selector performance, and small wire resistances of w- and b- lines. Improved from the conventional understanding, where only wire resistances of w- and b-lines are considered during writing, the proposed model includes the sneak currents even in the writing operation providing an even more comprehensive method of evaluating a RRAM device performance within the crossbar array picture than that of only the selectivity based read margin analysis.