Device-circuit co-design of memristor-based on niobium oxide for large-scale crossbar memory

Abstract

Memristor-based crossbar architecture emerges as a promising candidate for 3-D memory and neuromorphic computing. However, the sneak current through the unselected cells becomes a fundamental roadblock to their development, resulting in misreading and high power consumption. In this regard, we theoretically investigate the Pt/Ti/NbO2/Nb2O5−x/Pt-based self-selective memristor, which combines the inherent nonlinearity of the NbO2 switching layer and the non-volatile operation of the Nb2O5−x memory layer in a single device. The results show that the Pt/Ti/NbO2/Nb2O5−x/Pt-based self-selective memristor offers the sneak current of 310 nA, selectivity of around 174, and on/off current ratio of 75, compared to the sneak current of approximately 70 μA, selectivity of about 4.02, and on/off current ratio of around 1.55 for the Pt/Ti/Nb2O5−x/Pt-based memristor device. Our self-selective memristor minimizes the sneak current, but a small on/off current ratio limits their readout margin and power efficiency for crossbar array size greater than 4KB. Further, we demonstrate that breaking down a large-scale crossbar array into smaller subarrays and separating them by transistor switches, called the split crossbar array, is a more efficient way of achieving a practical size crossbar array with improved readout margin and power efficiency. Our results shed light on the potential of the Pt/Ti/NbO2/Nb2O5−x/Pt-based self-selective memristor and explore the split crossbar array architecture as a practical solution to augment readout margins and power efficiency in a large-scale crossbar array.