Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression

Abstract

Both 3D Vertical RRAM (VRRAM) and 3D Horizontal RRAM (HRRAM) architecture suffer from the issue of serious sneaking current, which leads to read or write disturbance and unacceptable power consumption waste, severely limiting its spatial stack-ability. In this work, the power consumption caused by sneaking current is separated out from the total set power consumption in HRRAM architecture. Then isolation cell structure is proposed to suppress the sneaking current. Simulation results show that total power consumption is reduced by about 30% with our proposed structure. Meanwhile, disturbance and read margin also show improvements.