Excess Voltage Research Articles

A new double multiplication region method to design high sensitivity and wide spectrum SPADs in standard CMOS technologies

Designing SPADs with high sensitivity in a wide wavelength range is crucial since the applications utilizing SPAD-based sensors target different parts of the spectrum. Here, we introduce a novel technique to achieve a wider sensitivity spectrum through the insertion of a second multiplication region into the depletion region. Thanks to the proposed method, at 5.5 V excess bias voltage, the fabricated devices achieved a PDP of 78% peak at 500 nm and 25.5% at 850 nm wavelength. At the same excess bias, we measured a normalized noise of 3.7 cps/μm2 and a jitter of 165 ps at 517 nm FWHM.

A Direct Current Self-Sustained Moisture-Electric Generator with 1D/2D Hierarchical Nanostructure for Continuous Operation of Off-Grid Electronics.

Ubiquitous moisture is a colossal reservoir of clean energy, and the emergence of moisture-electric generators (MEGs) is expected to provide direct power support for off-grid electronic devices anytime and anywhere. However, most MEGs rely on auxiliary energy storage devices and rectifier circuits to drive small electronic devices, which hinder scalability and widespread deployment, and the development of direct current (DC) MEGs with high power output that can directly drive off-grid electronic devices is highly promising but challenging. Herein, a self-sustained moisture-electric generator (SMEG) with a hierarchical nanostructure based on one-dimensional (1D) negatively charged nanofibers and two-dimensional (2D) conductive nanosheets was demonstrated to generate continuous DC electricity from atmospheric humidity. Sulfation of bacterial cellulose nanofibers lowers the surface potential and increases the surface charge energy, and reduced graphene oxide (rGO) provides a conduction pathway for electrons. The hierarchical nanostructures constructed by the combination of 1D nanofibers and 2D nanosheets endow the SMEG with self-sustained moisture gradients and structural anisotropy, which force the generation of a pseudocurrent. This combination also constructs microcapacitors that further enhance the moisture-electric power output. The SMEG can generate a continuous voltage in excess of 0.54 V for over 2160 h, with a power density of about 822 μW cm-3, demonstrating excellent operational durability. This research provides a feasible solution for the development of sustainable, versatile, and efficient power supplies for off-grid self-powered devices.

A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging.

Low-light imaging capabilities are in urgent demand in many fields, such as security surveillance, night-time autonomous driving, wilderness rescue, and environmental monitoring. The excellent performance of SPAD devices gives them significant potential for applications in low-light imaging. This article presents a 64 (rows) × 128 (columns) SPAD image sensor designed for low-light imaging. The chip utilizes a three-dimensional stacking architecture and microlens technology, combined with compact gated pixel circuits designed with thick-gate MOS transistors, which further enhance the SPAD's photosensitivity. The configurable digital control circuit allows for the adjustment of exposure time, enabling the sensor to adapt to different lighting conditions. The chip exhibits very low dark noise levels, with an average DCR of 41.5 cps at 2.4 V excess bias voltage. Additionally, it employs a denoising algorithm specifically developed for the SPAD image sensor, achieving two-dimensional grayscale imaging under 6 × 10-4 lux illumination conditions, demonstrating excellent low-light imaging capabilities. The chip designed in this paper fully leverages the performance advantages of SPAD image sensors and holds promise for applications in various fields requiring low-light imaging capabilities.

Pembuatan Prototype Pengereman Turbin Pada Pembangkit Listrik Tenaga Bayu Dengan Menggunakan Dummy Load Resistor

This study aims to develop a prototype braking system for wind turbines used in wind power plants by utilizing a dummy load resistor. The background of this research is the necessity for an effective braking system to control the speed of wind turbines, especially under extreme wind conditions, which can cause damage to the system and electrical components. The designed braking system uses a dummy load resistor to reduce the rotational speed of the turbine by dissipating excess electrical energy as heat. Tests were conducted to evaluate the effectiveness of the system under various wind conditions and to measure performance parameters such as turbine speed stability and protection of electrical components. The results show that the uses of dummy load resistors are effective in diverting excess voltage with a set point of 14 volts, and at 300 rpm using voltage sensors, proximity sensor and MOSFETs as voltage control, which will be diverted to the dummy load resistor system. Thus, this research makes a significant contribution to the development of wind power technology, particularly in terms of safety and operational efficiency.

The Effect of Soil Type on Touch Voltage and Step Voltage in the Grid Grounding System

The grounding system is one of the security systems in substations to channel excess voltage caused by lightning strikes that occur at substations, as well as electrical equipment. To design a grounding system, there are several factors that must be considered, including the type of soil, the configuration of the grounding system, the resistivity of the soil, and the condition of the surrounding environment. The aim of this research is to determine the safe limits in the substation grid grounding system which is influenced by the type of soil and influences the touch voltage and step voltage, which can be dangerous to humans. The method used is simulation with the Finite Element Method (FEM) in the ETAP application. Finite Element Method (FEM) is a method that uses image mediation by assuming that the grounding system is an equipotential structure. The test results were deliberately carried out with larger substation area parameters and different soil types, so that the differences between the influence and appearance of touch voltage and step voltage can be seen clearly.

Design of Solar Energy Based System Using Artificial Neural Network Controller

A key component of energy generation and the safe operation of the electrical system is solar energy. The solar energy system for producing the required voltage is presented in this paper. It is managed by an artificial neural network (ANN) controller, which performs significantly better than a conventional PI controller. It aids in lowering the system's total harmonic distortion (THD). The sole PI controller, which produces an erratic output response, is utilized in conventional wind turbines. It is swapped out in the suggested system for an ANN controller, which offers smooth voltage and current response. Two inputs and two outputs are used in the system's development. Six pulse-fired IGBTs that reduce excess voltage and current in the circuit operate this system. The MATLAB/Simulink tool was used to create the results, which were shown to be superior to traditional results. To regulate the impact of a variable power factor, an output variable load is connected. Every outcome has been validated and confirmed to be superior than traditional outcomes.

Room-temperature waveguide-coupled silicon single-photon avalanche diodes

Single photon detection is important for a wide range of low-light applications, including quantum information processing, spectroscopy, and light detection and ranging (LiDAR). A key challenge in these applications has been to integrate single-photon detection capability into photonic circuits for the realization of complex photonic microsystems. Short-wavelength (λ < 1.1 μm) integrated photonics platforms that use silicon (Si) as photodetectors offer the opportunity to achieve single-photon avalanche diodes (SPADs) that operate at or near room temperature. Here, we report the first waveguide-coupled Si SPAD. The device is monolithically integrated in a Si photonic platform and operates in the visible spectrum. The device exhibited a single photon detection efficiency of >6% for wavelengths of 488 and 532 nm with an excess voltage of <20% of the breakdown voltage. The dark count rate was below 100 kHz at room temperature, with the possibility of improving by approximately 35% by reducing the temperature to −5 °C.

Junction-Optimized SPAD With 50.6% Peak PDP and 0.64 cps/μm2 DCR at 2 V Excess Bias Voltage in 130 nm CMOS

Junction-Optimized SPAD With 50.6% Peak PDP and 0.64 cps/μm² DCR at 2 V Excess Bias Voltage in 130 nm CMOS

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization.

A Surge Absorber for the Sri Lankan Distribution Substation to Mitigate Lightning Damage

Due to high grounding resistance and soil conditions surge arrester performance decreases. Even though in installation the standard earthing resistance is achieved with time the earthing resistance would be at a high value. When a high voltage arrives at the surge arrestor it discharges the excess voltage by providing low impedance shunt path to ground and providing protection for the transformer. Because of high impedance path the voltage would not divert to the ground and carry on its original path and damage the transformer. Therefore, for areas with high earthing resistances protection must be improved for distribution substations. Throughout this research method of reducing the peak and the rate of rise of surge was analyzed for providing extra protection for the transformer. The selected substation was AV047 it was selected because of lightning occurrence in the selected area, Replacement of the transformer due to damages cause by overvoltage surges and high earthing resistance of the installed substation. Usage of the surge absorber for additional protection was investigated throughout the research. By this method proposed by the research group it was able to provide the sufficient protection for the transformer during surge conditions and reduce the peak and the rate of rise of the surge. Losses of the surge absorber were also analyzed at different conditions. Further an algorithm was developed so that the surge absorber could be implemented to any MV and HV networks for protection of the transformer.

Breaking Barriers to a Sustainable Future: Enhancing CO2 Reduction through Advanced Voltage Diagnosis

Electrochemical conversion of CO2 is a promising technology that uses renewable electricity to produce valuable chemicals with lower emissions than traditional methods. However, to make this technology commercially viable, it is crucial to run CO2RR at current densities higher than 200 mA/cm2, as determined by techno-economic analysis. This enables the amortization of electrolyzer capital costs over the typical operating lifetime of a potential commercial CO2RR facility. While the field has made progress in meeting this reaction rate target for many products of interest, reducing the operating voltage of CO2 electrolyzers remains a significant challenge. Addressing this challenge could pave the way for more efficient and cost-effective CO2RR technologies.The economic viability of CO2 electrolyzers heavily relies on their operating voltage, which is a crucial performance metric as it defines the energy efficiency of electrolyzers. Despite the importance of this metric, there is insufficient information on the distribution of voltage losses, especially in the membrane electrode assembly (MEA) electrolyzers as it is challenging to place a reference electrode in these configurations. Current research efforts focus on improving the performance of CO2 electrolyzers. Achieving industrially relevant current densities with high energy efficiency (EE) remains a challenge because full cell performance is impacted by several factors under the operating conditions. There is a need for cell diagnostics applicable to standard cell configurations that analyze each cell component (i.e., cathode, anode, and membrane) running under relevant conditions. In this study we aim to optimize the performance of the MEA systems and reduce operational voltage to enhance energy efficiency, which can address the high full-cell voltages of conventional CO2 electrolyzers and make them commercially viable and sustainable.In this study, we developed an analytical cell to measure voltage losses in a zero-gap MEA electrolyzer. This cell design incorporates reference electrodes on each side of the membrane, enabling it to measure both cathodic and anodic overpotentials. Electrochemical Impedance Spectroscopy (EIS) was also conducted to analyze the ohmic overpotential across the electrolyte. In the next step, the diagnostic platform was utilized to assess the performance of major CO2/COR approaches, including conventional Neutral CO2R in MEA and emerging high single pass aproaches COR, Acidic CO2R cell and CO2 Reactive capture system cell. In our analysis, we evaluated each system and identified the specific overpotentials associated with each cell component in each system. The voltage distribution plot highlights the key energy losses in each cell, indicating excess voltages required for each component. It reveals that CO2R in acidic media incurs significant voltage losses, primarily at the cathode/membrane interface. This finding emphasizes the need for optimization of this interface to reduce the overall energy loss and improve CO2RR efficiency. Additionally, we found that further optimization of the cathode and anode is essential to reduce the full cell voltage in CO2 reactive capture approach. Our analysis also demonstrates that COR approach is a very promising approach as it exhibits the lowest cathode and anode overpotentials.In conclusion, our study highlights the significance of minimizing energy losses in CO2RR for enhanced efficiency and feasibility. The voltage distribution plot can serve as a useful tool for identifying and addressing critical energy losses in each cell component. Figure 1

Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications.

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.

Study of the influence of virtual guard ring width on the performance of SPAD detectors in 180 nm standard CMOS technology

The influence of the virtual guard ring width (GRW) on the performance of the p-well/deep n-well single-photon avalanche diode (SPAD) in a 180 nm standard CMOS process was investigated. TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1 μm. It is experimentally found that, compared with an SPAD with GRW = 2 μm, the dark count rate (DCR) and afterpulsing probability (AP) of the SPAD with GRW = 1 μm is significantly increased by 2.7 times and twofold, respectively, meanwhile, its photon detection probability (PDP) is saturated and hard to be promoted at over 2 V excess bias voltage. Although the fill factor (FF) can be enlarged by reducing GRW, the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling (TAT) effect in the 1 μm guard ring region. By comparison, the SPAD with GRW = 2 μm can achieve a better trade-off between the FF and noise performance. Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.

Validation of Electrical Noise of a DC Motor through Controlled Varistor Cracking: An Experimental Study

The varistor is an electronic component that protects the DC motor’s circuitry from electrical noise or transients that can cause damage. It works as a voltage-dependent resistor that can change its resistance according to the applied voltage. Once the voltage surpasses a specific threshold, the varistor conducts and directs the excess voltage away from the motor’s circuitry. In small DC motor manufacturing, ring varistors are vital for reducing electrical noise, minimizing spark-induced damage to the commutator and brush, and extending the motor’s lifespan. Additionally, they prevent damage to electronic parts in the customer’s mechanism set. The objective of this study is to investigate the impact of varistor cracks or chips that may occur during the soldering process of varistors to the commutator. To confirm the occurrence of cracks or chips, intentional damage will be inflicted on the varistors. The study aims to determine how the presence of cracked or chipped varistors affects the electrical noise produced by a DC motor during its operation. The resulting spark was observed through an oscilloscope, and it was found that the effect could be substantial, up to 5 to 10 times the rated voltage supplied to the motor. In the next phase of this study, further tests will be conducted on motors without varistors to provide a comparison.

Microgrid Design in Electricity Supply in Paper Factories

Renewable energy is growing, one of which is by controlling solar energy. A solar power plant (PLTS) is a power generation system that utilizes solar energy to become electrical energy through photovoltaic modules, which are included in environmentally friendly energy so that it becomes a renewable, effective, more efficient, and reliable plant. The research designing the modeling of PLTS on a grid was carried out on the roof of a gas power plant (PLTG) which generated 164.47 MWh / year. Analyzing modeling in the addition of the Rooftop Solar System that enters the network can reduce exhaust emissions from the use of other equipment for four years with an average of PLN by 99.29%, PLTG #1 by 99.06 and PLTG #2 by 99.11%. The impact of the addition of the PLTS Rooftop on the quality of power entering the 3.3 kV network system is seen that the feeder 2-panel bus has improved to 97.82% of the voltage drop of 72.67% in line with the PLN 3 panel, the improvement is made by providing capacitors of 3x4Mvar. Feeder 3 improved to 97.61% of the voltage drop of 78.87%, in line with the PLN 4 panel. The improvement was carried out by providing a capacitor of 2x4Mvar. Panel feeder four was seen to have improved to 99.21% from an excess voltage of 109.23% in line with the generating equipment, and the improvement was made by reducing capacitors by 0.1 Mvar from the used 5x0.1 Mvar.

Switched-Resistor Passive Balancing of Li-Ion Battery Pack and Estimation of Power Limits for Battery Management System

The battery pack performance and expected lifespan are crucial in electric vehicle applications. Balancing the charge on a battery pack connected in series and parallel is crucial due to manufacturing discrepancies and distinct performance of each cell in a standard battery pack. In this paper, a switched-resistor passive balancing-based method is proposed for balancing cells in a battery management system (BMS). The value of the available voltage at the battery cell terminals is balanced using resistors in an electrical circuit, and the excess voltage is eliminated. The cell balancing outcome demonstrates that the electrical circuit can maintain an even voltage across each cell. The procedure of balancing involves individually adjusting each cell’s level of charge. Passive balancing releases energy as heat by draining charge from cells that have too much charge. A passive cell balancer is a cost-effective solution and easy to install, but due to thermal loss from a resistor, it has a low energy efficiency for cell balancing and necessitates a lengthy balancing process. This passive cell balancer is an effective and reliable method for low-power devices and portable applications such as electrical vehicles. The power limits during charging and discharging are estimated using the bisection method.

Single-photon avalanche diode fabricated in standard 55 nm bipolar-CMOS-DMOS technology with sub-20 V breakdown voltage.

This paper presents a single-photon avalanche diode (SPAD) in 55 nm bipolar-CMOS-DMOS (BCD) technology. In order to realize a SPAD having sub-20 V breakdown voltage for mobile applications while preventing high tunneling noise, a high-voltage N-well available in BCD is utilized to implement the avalanche multiplication region. The resulting SPAD has a breakdown voltage of 18.4 V while achieving an excellent dark count rate of 4.4 cps/µm2 at the excess bias voltage of 7 V in spite of the advanced technology node. At the same time, the device achieves a high peak photon detection probability (PDP) of 70.1% at 450 nm thanks to the high and uniform E-field. Its PDP values at 850 and 940 nm, wavelengths of interest for 3D ranging applications reach 7.2 and 3.1%, respectively, with the use of deep N-well. The timing jitter of the SPAD, full width at half maximum (FWHM), is 91 ps at 850 nm. It is expected that the presented SPAD enables cost-effective time-of-flight and LiDAR sensors with the advanced standard technology for many mobile applications.

Quenching Circuit Discriminator Architecture Impact on a Sub-10 ps FWHM Single-Photon Timing Resolution SPAD

In the field of radiation instrumentation, there is a desire to reach a sub-10 ps FWHM timing resolution for applications such as time-of-flight positron emission tomography, time-of-flight positron computed tomography and time-resolved calorimetry. One of the key parts of the detection chain for these applications is a single-photon detector and, in recent years, the first single-photon avalanche diode (SPAD) with a sub-10 ps timing resolution was presented. To reach such a timing resolution, the SPAD was read out by an operational amplifier operated in open-loop as a comparator. This paper presents a comparison between comparators and inverters to determine which type of leading-edge discriminator can obtain the best single-photon timing resolution. Six different quenching circuits (QCs) implemented in TSMC 65 nm are tested with SPADs of the same architecture and in the same operation conditions. This allows us to compare experimental results between the different QCs. This paper also presents a method to measure the SPAD signal slope, the SPAD excess voltage variation and simulations to determine the added jitter of different leading-edge discriminators. For some discriminator architectures, a cascode transistor was required to increase the maximum excess voltage of the QC. This paper also presents the impact on the single-photon timing resolution of adding a cascode transistor for a comparator or an inverter-based discriminator. This paper reports a 6.3 ps FWHM SPTR for a SPAD read out by a low-threshold comparator and a 6.8 ps FWHM SPTR for an optimized 1 V inverter using a cascode transistor for a higher excess voltage.

Comparative Single Photon Time Resolution Measurements of Commercial Silicon-Photomultipliers and a Specially Designed SiPM with High Accuracy in 0.35 µm Technology

In this study, we present highly accurate single photon time resolution (SPTR) measurements of proved commercial Silicon-Photomultiplier (SiPM) from Broadcom (AFBR-S4N44C013), KETEK (PM3350), OnSemi (FJ30035) and Hamamatsu (S13360-3050V) with similar dimensions for highly precise SPTR measurements. The principal objective of this project was to investigate the timing precision of SiPM, since they play a key role for users in application areas like time of flight positron emission tomography (TOF-PED). For the SPTR comparative measurements in this research, we used a high-precision measurement setup including a femtosecond laser (λ = 400 nm, pulse width = 70 fs) and an oscilloscope with a 10 GHz bandwidth and a sampling rate of 50 GS/s to keep the influence of the measurement setup on the SPTR as small as possible, so that we are able to measure the true SPTR of commercial SiPM. In order to filter out external noise, we present an offline analysis to get as close as possible to the intrinsic SPTR of each SiPM. Furthermore, this study presents a special designed 4 x 4 SiPM integrated into a 0.35 µm CMOS process. The CMOS SiPM consists of a moderately selected diode capacitance combined with a low grid capacitance leading to very short pulses with a peak width below 2 ns and a peak height of 30 mV at an excess bias voltage of 8 V, facilitating the acquisition without the requirement of a pre-amplifier. The final obtained SPTR results of the commercial SiPM showed values between 191 ps to 104 ps. For the 4 x 4 CMOS SiPM a SPTR of 40 ps was achieved. We also show that SPTR values can be improved by filtering out external noise by a subsequent offline analysis up to 55.5%.

Design and Characterization of n/p-well CMOS SPAD With Low Dark Count Rate and High Photon Detection Efficiency

We have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).