Voltage-controlled Oscillator Research Articles

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

K‐band CMOS voltage‐controlled oscillator using switched self‐biasing technique

AbstractA complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a 65‐nm CMOS process. The measurement results of the proposed VCO showed a frequency tuning range from 22.57 to 25.3 GHz, and a phase noise of −108.48 dBc/Hz at a 1‐MHz offset frequency with a power consumption of 8.27 mW at a supply voltage of 1.2 V. The calculated figure of merit (FoM) and FoM with the tuning range were −186.48 and −187.67 dBc/Hz, respectively.

The Influence of Viscosity on Heat Dissipation under Conditions of the High-Frequency Oscillating Magnetic Field

High-frequency components such as microprocessors, transistors, antennas, voltage-controlled oscillators, and many others generate a large amount of heat. In the absence of satisfactory cooling, these components may suffer damage or even destruction. Therefore, it is important to find effective ways to cool these components. A possible solution is to use oil-based magnetic fluids. Magnetic fluids contain magnetic particles dispersed in oil, and their properties, including viscosity, affect their cooling capabilities. Viscosity can be changed by adding various additives or by adjusting the concentration of magnetic particles. The advantage of using oil-based magnetic fluids for cooling is that they allow for precise dosing and control of the amount of fluid applied to the component, reducing thermal losses and increasing cooling efficiency. In addition, oil-based magnetic fluids can also act as a dielectric, reducing electrical noise and increasing electromagnetic compatibility with the components. Analyzing the heating rate of magnetic fluids consisting of mineral oils in an alternating magnetic field with a frequency of 500 kHz, we have shown the capability of controlling thermal losses by adjusting the viscosity of the carrier liquid.

Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology

This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 [Formula: see text]W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique.

A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique

This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based ΔΣ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW.

180 nm NMOS voltage-controlled oscillator for phase-locked loop applications

<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.</p>

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

A deep neural network architecture for the automatic sizing of analog circuit components is proposed, with a focus on radio frequency (RF) applications in the 2 to 5 GHz region. It addresses the challenges of the typically small number of examples for network training and the existence of multiple solutions, of which impractical values for integrated circuit implementation. We address these issues by restricting the learning to one component size at a time, thanks to a cascade of dedicated shallow neural networks (SNN), where each network constrains the prediction of the next ones. Moreover, the SNNs are individually tuned by a genetic algorithm for the prediction order and accuracy. This reduction of the solution space at each step allows the use of small training sets, and the introduced constraints between SNNs handle component interdependencies. The method is successfully validated on three different types of RF microcircuits: a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer, using 180 nm and 130 nm CMOS implementations. All the predictions were within 5 % of the true values, both at the component and performance levels, and all the responses were obtained in less than 5 s, after 4 to 47 min. training on a regular PC station. The obtained results show that the proposed method is fast and applicable to arbitrary analog circuit topologies, with no need to retrain the developed neural network for each new set of desired circuit performances.

Single-phase binary phase-shift keying, quadrature phase shift keying demodulators using an XOR gate as a phase detector

A single-phase/single-loop multiple-phase-shift-keying (<em><span lang="EN-US">m</span></em><span lang="EN-US">-PSK)</span><span lang="EN-US"> demodulator is described. The demodulator relies on a linear range of an exclusive-OR (XOR) gate employed as a phase detector. The phase controller takes the average output from the XOR gate and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for an </span><em><span lang="EN-US">m</span></em><span lang="EN-US">-PSK signal. The proposed single-phase binary-/quadrature-PSK (BPSK/QPSK) demodulators have been implemented with low-cost discrete components. The core of the phase controller simply relies on number of stages of a full-wave rectifier and a linear amplifier built from well-known op-amp-based negative feedback circuits. The demodulator prototypes operate from a single supply of 5 V. At a carrier frequency of 100 kHz, both the BPSK and QPSK demodulators achieved the maximum symbol rate of 20 ksymbol/s respectively. At these symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 2×10<sup>-10 </sup>and 7×10<sup>-10</sup>.</span>

A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator

A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flip-flop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18<em>-</em>mm digital complementary metal–oxide–semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10<sup>-10</sup> and 9.8×10<sup>-10</sup>, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ.

A 223–276-GHz Cascadable FMCW Transceiver in 130-nm SiGe BiCMOS for Scalable MIMO Radar Arrays

This article reports a 223–276-GHz monostatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) chip. The TRX is suitable for building massive multiple-input multiple-output (MIMO) radar arrays in the daisy-chain topology because of its cascadable feature based on the injection-locking feedthrough technique. The TRX is based on 18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> frequency multiplication chain that can be fed by either an external signal generator (SG) or its internal voltage-controlled oscillator (VCO). The modulation bandwidth (BW) is about 53 GHz when the internal VCO is activated, resulting in a range resolution of better than 3 mm. The peak output power is 3.1 dBm at 240 GHz with a 3-dB BW of 41 GHz. Its receiver (RX) channel is based on the in-phase/quadrature architecture enabling complex signal sampling. The minimum single-sideband (SSB) noise figure (NF) is 18.7 dB at 255 GHz, and the average value is 20.7 dB. The TRX chip includes an on-chip antenna coupled with a silicon lens, offering a peak effective isotropic radiated power (EIRP) of 27 dBm at 240 GHz. The TRX consumes a dc current of 234 and 270.1 mA from a single supply voltage of 3.3 V for external and internal VCO operations, respectively. The chip occupies a total area of 2.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1.26 mm).

Design and Analysis of a Low-Voltage VCO: Reliability and Variability Performance.

This paper investigates an adaptive body biasing (ABB) circuit to improve the reliability and variability of a low-voltage inductor-capacitor (LC) voltage-controlled oscillator (VCO). The ABB circuit provides VCO resilience to process variability and reliability variation through the threshold voltage adjustment of VCO's transistors. Analytical equations considering the body bias effect are derived for the most important relations of the VCO and then the performance is verified using the post-layout simulation results. Under a 0.16% threshold voltage shift, the sensitivity of the normalized phase noise and transconductance of the VCO with the ABB circuit compared to the constant body bias (CBB) decreases by around 8.4 times and 3.1 times, respectively. Also, the sensitivity of the normalized phase noise and transconductance of the proposed VCO under 0.16% mobility variations decreases by around 1.5 times and 1.7 times compared to the CBB, respectively. The robustness of the VCO is also examined using process variation analysis through Monte Carlo and corner case simulations. The post-layout results in the 180 nm CMOS process indicate that the proposed VCO draws a power consumption of only 398 µW from a 0.6 V supply when the VCO frequency is 2.4 GHz. It achieves a phase noise of -123.19 dBc/Hz at a 1 MHz offset and provides a figure of merit (FoM) of -194.82 dBc/Hz.

A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ABSTRACT This paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of −77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves −59.7 dBc. It measures the 1.2 s settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 s settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is −105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.

High-precision fiber-optic time transfer with an unlimited compensation range.

We present a fiber-optic time transfer system with high transfer stability and an unlimited compensation range of the delay variation. We first stably transmit a frequency signal from a voltage-controlled oscillator to the remote site. The time signal is then embedded in the frequency signal by simply selecting its one cycle per second with a tunable gate signal. Therefore, the proposed time transfer system inherits both the stability and the unlimited adjustment range of the frequency transfer yet with no need for demodulation. The time deviation of 1.93 ps is achieved at 1000-s averaging. This simple and demodulation-free time transfer system is applicable for scalable distributed applications that require high-precision time synchronization and wide-range delay compensation.

A 20.65-to-40.55 GHz Dual-Core Quad-Mode VCO With Mode-Independent Transformer-Switching Technique in 65-nm CMOS

This paper proposes a dual-core quad-mode millimeter-wave (mm-wave) voltage-controlled oscillator (VCO) using a compact multi-mode LC network with a modeindependent switched transformer technique. On top of the dualmode main LC tank, the mode-independent switched transformer technique introduces two additional oscillation modes, further extending the frequency tuning range with a small chip area overhead, while the mode-independent feature reduces the cost of switch off-capacitance compared with the conventional switched transformers. Implemented in 65nm CMOS process, the proposed VCO achieves a measured octave frequency tuning range from 20.65 to 40.55 GHz. The measured best phase noise is -131.04 dBc/Hz at 10 MHz offset from 20.65 GHz. The measured best figure-of-merit (FoM) is 187.25 dBc/Hz at 10 MHz offset from 26.66 GHz, corresponding to a figure-of-merit of tuning range and area (FoMTA) of 216.72 dBc/Hz thanks to the proposed compact multi-mode LC network and the mode-independent switched transformer technique. The VCO consumes 9.75-to-18.85 mW from a 0.65 V supply voltage. The core area is 0.048 mm2.

A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS

A new four-frequency-shift keying (4FSK) transceiver (TRX) at 145–185-GHz operation frequency is presented. The proposed non-coherent TRX is a fully integrated bit-in–bit-out communication system without the need for separate modulators/demodulators (modems). The transmitter (TX) core includes only one voltage-controlled oscillator (VCO), which can generate four different frequencies based on the two parallel streams of binary data at its input. The receiver (RX) with a frequency overlapping architecture demodulates the 4FSK signal and recovers the two parallel streams of binary data. Both the TX and the RX are designed and fabricated in a standard 65-nm CMOS process. The TX and RX consume 62-and 120-mW power, respectively. The highest achieved data rate is 17 Gb/s at an 18-cm link distance with 10.7-pJ/bit energy efficiency.

Systematic Design of a Pseudodifferential VCO Using Monomial Fitting

Digital integrated electronics benefits from its higher abstraction level, allowing optimisation methods and automated workflows. However, analogue integrated circuit design is still predominantly done manually, leading to lengthy design cycles. This paper proposes a new systematic design approach for the sizing of analogue integrated circuits to address this issue. The method utilises a surrogate optimisation technique that approximates a simple monomial function based on few simulation results. These monomials are convex and can be optimised using a simple linear optimisation routine, resulting in a single global optimal solution. We show that monomial functions, in many cases, have an analytic relation to integrated circuits, making them well suited for the application. The method is demonstrated by designing a 14 MHz pseudodifferential voltage-controlled oscillator (VCO) with minimised current consumption and is manufactured in a 180 nm process. The measured total current matches the predicted and is lower than that for other similar state-of-the-art VCOs.

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

This article introduces a novel approach of hybrid current-starved ring voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications. In this, two novel VCO designs are proposed. The first design is the current starved pull-up sleepy ring VCO which offers improved frequency of oscillation and reduced phase noise. The second design utilizes a hybrid current starved ring VCO with the bulk-driven keeper technique which yields better results by reducing the power consumption and mitigating leakage current. The proposed circuit is analysed with various process corners and performs parametric analysis and Monte-Carlo analysis to verify the robustness of the circuit using Cadence Virtuoso tool with 45 nm gpdk library. The average power of the proposed −2 circuit is 7.38 µW, and it achieves an oscillation frequency of 6.965 GHz at 1 V supply. It has low phase noise of −121.49dBc/Hz at 1 MHz, and the output noise of −166.42 dB. The obtained figure of merit (FOM) is −185.95dBc/Hz. The proposed design exhibits a frequency tuning range of 92.8 %. The results clearly demonstrate that the proposed design is extremely tolerant to PVT (process, voltage, and temperature) variations making it well suitable for high-frequency PLL applications.

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.