Voiding In Interconnects Research Articles

Critical Temperature Shift for Stress Induced Voiding in Advanced Cu Interconnects for 32 nm and Beyond

Work showing evidence of a shift in the Stress Migration (SM) peak profile temperature for smaller interconnect linewidths typically associated with the 32nm technology node and beyond is presented here. With other parameters (fabrication, materials, line thickness and via diameter being kept nominal among all these samples), this clear shift towards the lower temperatures for smaller linewidths appear to indicate a size effect in the Stress Migration in advanced Cu interconnect scheme. The synchrotron x-ray micro-diffraction experiment, is used to show that plasticity is involved in the stress relaxation process at about 200° C, but not at higher temperature nor at room temperature. Such plasticity-assisted strain relaxation in interconnects especially at lower temperature range could explain the critical temperature shift observed in the present study, in addition to the typical diffusion-assisted mechanism. Further, the synchrotron X-ray micro-diffraction experiments also suggests indications of plasticity-assisted voiding. Numerical finite element analyses were also conducted in conjunction with the experimental study, to provide greater insight. The modelling result demonstrates the importance of creep plasticity in causing thermal stress relaxation in Cu interconnects.

Analysis of Resistance Change Development Due to Voiding in Copper Interconnects Ended by A Through Silicon Via

The resistance change due to electromigration induced voiding in modern copper interconnects ended by a Through Silicon Via (TSV) is analyzed. It is shown that two different modes of resistance increase exist during the period of void growth under the TSV. Primarily responsible are imperfections at the TSV bottom introduced during the fabrication process. Consequently, the time to failure of such structures under electromigration stress is likely to follow a bimodal distribution. An analytical model is proposed to explain the resistance change development based on published experimental data and also on numerical simulations.

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress, which is critical to the formation of stress-induced voiding (SIV) in copper damascene interconnects. Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry. In addition, hydrostatic stress is studied through the influences of different low-k dielectrics, barrier layers and line widths of copper lines, and the results indicate that hydrostatic stress is strongly dependent on these factors. Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.

Structure-dependent behavior of stress-induced voiding in Cu interconnects

Stress modeling and cross-section failure analysis by focused-ion-beam have been used to investigate stress-induced voiding phenomena in Cu interconnects. The voiding mechanism and the effect of the interconnect structure on the stress migration have been studied. The results show that the most concentrated tensile stress appears and voids form at corners of vias on top surfaces of Cu M1 lines. A simple model of stress induced voiding in which vacancies arise due to the increase of the chemical potential under tensile stress and diffuse under the force of stress gradient along the main diffusing path indicates that stress gradient rather than stress itself determines the voiding rate. Cu interconnects with larger vias show less resistance to stress-induced voiding due to larger stress gradient at corners of vias.

The temperature characteristics of stress-induced voiding in Cu interconnects

A stressinduced voiding model based on the NabarroHerring mechanism has been proposed. The stressinduced voiding phenomena in Cu interconnects have been studied by the FIB crosssection technique and stress modeling. The driving force for the formation of stressinduced voids has been investigated. The relationship between stressinduced voiding, temperature, stress gradient and the dominant diffusion path are discussed. The results show that stress and stress gradient reach their peak values at the top surfaces of Cu M1 lines underneath the corner of the vials where voids are observed. Stress gradient shows crucial effect on the failure spot and the voiding rate. Stress migration is basically a diffusion and nucleation process of vacancies through the main diffusion path under the force of the stress gradient. The stress gradient and the diffusion terms vary oppositely with temperature and the maximum voiding rate is reached at a medium temperature.

Temperature-dependent stress-induced voiding in dual-damascene Cu interconnects

Temperature-dependent stress-induced voiding (SIV) of Cu dual-damascene interconnects in via-line structures has been studied by stress modeling and focused-ion-beam (FIB) cross-section analysis. The via-line structures have been studied at temperatures ranging from 100 to 250 °C, with highest voiding rate being detected at 200 °C. The hydrostatic stress and stress gradient reach each peak values and lead to void nucleation symmetrically underneath the edge of the via. Stress gradient instead of stress shows crucial effect on the SIV process. Voids tend to grow horizontally along the Cu/SiN interface under larger stress gradient in the line length direction as compared to the line height direction. A voiding model based on Nabarro–Herring equations has been proposed and the relation between the voiding rate and stress gradient has been built. The voiding model shows that the stress-induced voiding is a process by which vacancies diffuse and concentrate to form voids under the force of stress gradient. The stress and the diffusional factors grow oppositely with temperature and the maximum voiding rate is reached at a medium temperature.

The effect of via size on the stress migration of Cu interconnects

Accelerated stress-migration testing under 200℃ of Cu (M1/M2) interconnects has been done for 700h. Finite element analysis and focused-ion beam techniques have been used to study the stress-induced voiding in the Cu interconnects with vias of 500 and 350nm in diameter. The voiding mechanism and the effect of via size on the stress migration have been studied. The results show that peak values of stress and stress gradient in M1 lines are reached underneath the edge of vias. The stress gradient shows crucial effect on the voiding process. The vacancies introduced by thermo-mechanical stress diffuse along Cu M1/SiN interfaces under the force of stress gradient and nucleate at the peak values of the stress gradient. The void grows faster along the length direction because the stress in M1 lines changes faster horizontally. The stress and stress gradient increase with increasing via diameter, leading to a faster voiding rate.

Reliability issues in Cu/low- k structures regarding the initiation of stress-voiding or crack failure

Continuous down scaling of the interconnect dimensions led to the introduction of copper and low- k dielectric materials. The use of such materials is challenging in the field of mechanical reliability, such as stress-induced voiding in copper interconnects and cracking of low- k dielectrics. Up to now these two failure modes were investigated separately. However, recent experimental observations tend to demonstrate the possibility of a complex interaction between these both failure modes, one overwhelming or enhancing the other. In this paper, a comparison of the risk of void or crack occurrence is made by mean of finite element modeling. Further, the interaction between these two failure modes (voiding and cracking) is also studied.

The influence of temperature and dielectric materials on stress induced voiding in Cu dual damascene interconnects

In this work, package level stress migration test of Cu dual-damascene interconnects in via-line structures was performed. The effects of stressing temperature and dielectric materials on SIV behavior were investigated. The via-line structures were studied at temperatures ranging from 150 to 250 °C, with highest failure rate being detected at 200 °C. In comparing stress migration data on carbon doped oxide (CDO) with undoped silica glass (USG), a difference of two orders of magnitude was detected in the rate of change of resistance. About 40% of the CDO samples showed open circuit failures after a 1344-h test, whereas the maximum resistance change in the USG samples was only 10%. Failure analysis indicated that failures in both CDO and USG were very similar in nature. In both cases, voids formed symmetrically at the bottom of the via, showing that the integrity of the Ta barrier in the via bottom area was of significant influence to stress induced voiding. Finite element analysis (FEA) indicated that the driving force for void growth, the gradient of hydrostatic stress, at via bottom in CDO structure is 30% higher than the one in USG. Besides the stress gradient, other factors that could affect SIV behaviour are the back stress and interface adhesion. Similar to the case of electromigration, back stress might be generated during stress migration, provided that the interface between the Cu line and the surrounding dielectric material is strong. Back stress reverses the trend of migration of atoms. Discussion and comparison of all these factors are made between the two types of dielectrics in order to explain the observed higher failure rate of stress-induced-voiding in CDO structures.

The effect of line width on stress-induced voiding in Cu dual damascene interconnects

The influence of M1 (lower level Cu) line width on stress-induced voiding (SIV) behavior of copper dual damascene interconnects was investigated by stress migration test at 200 °C and finite element analysis (FEA). M1 line width under study ranged from 200 nm to 1000 nm, whereas the M2 line width was fixed to be 3 μm. The normalized change in resistance indicated that the via-line structures with larger M1 line width were more susceptible to SIV. Failure analysis utilizing focus ion beam (FIB) showed that voids were formed in the via bottom region for samples with M1 line width less than 280 nm. However, voids were found at the Si 3N 4/M1 Cu interface near the via bottom if M1 line width is larger than 280 nm. To further understand the underlying physics of SIV, three dimensional finite element models were built to simulate the hydrostatic stress distribution in the via-line structures. It was found that the stress gradient in the length direction, grad σ l, was not sensitive to M1 line width, however, the stress gradient in the line width direction, grad σ w, was found to increase with M1 line widths. It is thus proposed that in addition to the active diffusion volume, it is the grad σ w that further favors the migration of voids (or vacancies) along the Si 3N 4/M1 Cu interface and subsequent accumulation of the voids near the via bottom leading to a much higher resistance change at larger M1 widths.

A physically based lifetime model for stress-induced voiding in interconnects

We use a simple closed-form lifetime model for stress-induced voiding (SIV) or stress migration for Al- or Cu-based interconnects. Stress-induced voiding is treated as a process of void nucleation/growth and stress relaxation through atomic diffusion driven by a stress gradient. We developed a physically based method of modeling atomic diffusion and void growth, which explicitly accounts for the dependence of void growth on several factors including stress, temperature, diffusivity, and effective modulus. Based on basic physics associated with void growth, we define zones as SIV plate, SIV long line, and SIV short line, respectively, i.e., the three sequential stages for the process of void growth, depending on a nondimensional time-dependent parameter ψ and the aspect ratio of the interconnect. Simple form solutions to the governing equations that describe void growth are then sought for each scenario separately. Time to failure (TTF) is calculated as a function of stressing temperature, mechanical stress, interlayer dielectrics property, and line dimension based on an explicit formulation. The model provides insight into the separate impact of each input factor upon the SIV rate. We find that TTF is invariant with line width in the early zone (SIV plate), while void generation rate is linear with time. TTF is a strong function of line width for both the later zones. The void generation rate varies as the square root of time in the SIV long-line realm, but is constant with time in the SIV short-line zone.

Grain boundary grooving and cathode voiding in bamboo-like metallic interconnects by surface drift diffusion under the capillary and electromigration forces

The process of grain boundary (GB) grooving and cathode voiding in sandwich type thin film bamboo lines are simulated by introducing a mathematical model, which flows from the fundamental postulates of irreversible thermodynamics. In the absence of the electric field, the computer studies on the triple junction kinetics show that it obeys the first order reaction kinetics at early transient stage, which is followed by the familiar time law as t¯1∕4, at the steady state regime. The applied electric field (EF) in constant current experiments modifies this time law drastically above the well-defined electron wind intensity (EWI) threshold, and puts an upper limit for the groove depth, which decreases monotonically with EWI. Below the threshold level, the capillary regime predominates, and EF has little effect on the general kinetics of GB grooving, other than the linear increase in total elapsed time with EWI. An analytical formula for the cathode failure time in constant voltage test is obtained in terms of the system parameters, which are closely associated with the cathode voiding or grain thinning by surface drift diffusion.

Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Stress-induced voiding (SIV) is a serious problem in Cu dual-damascene interconnects (DDIs). The stress gradient under vias is the driving force of vacancy diffusion and void generation, therefore stress control in Cu-DDI is an important factor for suppressing SIV. In this study, the stress effect of upper Cu film on SIV in lower Cu lines is investigated, and the stress distribution in Cu-DDI is analyzed by finite element analysis. It is found that SIV in the lower Cu lines is strongly affected not only by the width of lower lines but also by the metallurgical properties of the Cu film in upper metals. Suppression of tensile stress in the via of the upper Cu film decreases the stress gradient in the lower line around the via, and eventually, the driving force of vacancy diffusion to the via bottom. Control of the metallurgical properties to suppress Cu creep during annealing is a key factor for decreasing SIV in lower Cu lines. High-temperature deposition of Cu film with a small coefficient of thermal expansion (CTE) is a solution to suppressing SIV failure in Cu-DDIs.

Mechanism of reliability failure in Cu interconnects with ultralow-κ materials

This letter presents evidence of an oxidation-driven failure mechanism in Cu interconnects integrated with ultralow-κ materials. It is found that the open pore structure of ultralow-κ materials allows oxidants in the ambient to reach the interconnect structure and induce oxidation of Cu. In contrast to a normal oxidation process where Cu is in contact with the oxidant, oxidation is controlled by the outdiffusion of Cu through the barrier layers, Ta and SiCN, to form Cu oxide in the pores of the dielectric material. The loss of Cu by outdiffusion induces extensive voiding and subsequent failure in Cu interconnects.

3-Dimensional Elastic-Plastic Finite Element Analysis of Stress-Induced Voiding in Cu Damascene Interconnects of Ultra-Large-Scale Integrated Circuits

In order to discuss stress-induced voiding (SIV) of Cu damascene interconnect structures in ultra-large-scale integrated circuits (ULSls), 3-D elastic-plastic finite element analysis (FEA) was carried out based on stress-temperature behavior of constituent thin films measured by a wafer curvature method. Two types of Cu interconnect geometries with either D-SiN cap/p-SiON etch-stop layers or D-SiCN : H cap/p-SiC : H etch-stop layers were analyzed. The effect of the Cu line width was also investigated. It was found from the FEA results that, regardless of the geometry, the hydrostatic tensile stress of Cu in the structure with D-SiCN : H/p-SiC : H layers was generally lower than that with p-SiN/p-SiON layers. It was also expected that, for the structure with p-SiN/p-SiON layers, SIV is most likely to occur near the via center while for the structure with p-SiCN : H/p-SiC : H layers, it is most likely to occur near the via bottom. In the structure with D-SiCN : H/p-SiC : H layers, it was considered that a larger line width is susceptible to voiding in the via due to a high hydrostatic stress gradient in the via and a high magnitude of equivalent plastic strain in the line.

Stress-induced and electromigration voiding in aluminum interconnects passivated with silicon nitride

Void nucleation in aluminum interconnects passivated with silicon nitride was studied using a high voltage scanning electron microscope. Extensive stress-induced voiding was observed in these interconnects independent of the passivation thickness. Some of the stress-induced and electromigration-induced voids formed away from the interconnect sidewall in contrast to results from other studies of void nucleation in passivated aluminum lines. Nuclear reaction analysis measured large amounts of hydrogen in the aluminum films passivated with silicon nitride. Transmission electron microscopy showed a high density of nanometer-sized bubbles in the aluminum. These bubbles, which are thought to have formed from hydrogen that evolved from the silicon nitride layer during processing, served as nucleation sites for stress- and electromigration-induced voids.

Effect of Texture on Hillock Formation in Aluminum Films

AbstractStress voiding describes a phenomenon in thin interconnect lines where hillocks and voids are formed during thermal cycling due to the stresses caused by the difference in the thermal expansion coefficients of metal used in the interconnect lines and the substrate material. The effect of texture on stress voiding in aluminum interconnects is investigated using orientation imaging microscopy (OIM© ) and scanning electron microscopy. Aluminum films were deposited by PVD deposition onto sublayers of Ti and Ti plus TiN and were analyzed for crystallographic texture and grain boundary structure using OIM©. These films were later annealed at 400°C for 1 hour and cooled. The specimens were examined for the presence of hillocks and voids using a scanning electron microscope. The results show strongly textured (111) films are more resistant to hillock and void formation.

Stress Voiding in IC Interconnects—Rules of Evidence for Failure Analysts

Abstract This is the second article in a two-part series on the causes of stress voiding and the evidence required to tie it to an IC interconnect failure. The first part, published in the November 1999 issue of EDFA, focuses on the causes and distinguishing characteristics of stress void failures. Here, that information is applied in the analysis of an actual case of stress voiding. The author explains how he developed evidence of stress, nucleation, and diffusion, the three phenomena required to differentiate stress voiding from other failure mechanisms, and how this evidence pointed to specific processing errors and suggested how to fix them. Although the investigation relied heavily on traditional observational tools, they were applied in new ways using a relatively new technique, FIB backside thinning, to gain critical proof of nucleation and confirm suspected processing errors.

Dislocation pile-ups as sites for formation of electromigration-induced transgranular slit-like voids in Al interconnects

Electromigration-induced voiding in metal interconnects in Si integrated circuits is a serious reliability concern. The microstructure of narrow interconnects subject to post-pattern anneal is expected to be bamboo-like in character. These structures are best described as chains of single crystals, with grain boundaries perpendicular to the interconnect axis. In these microstructures, two distinct types of void morphologies have been reported in Al-alloy interconnects: large, wedge shaped erosion voids (E-voids), and narrow slit-like voids (S-voids). A summarized below, electromigration experiments conducted on single-crystal Al interconnects have clearly shown that the transition of erosion voids to slit-like voids is very strongly dependent on the crystallography of the interconnect, and also that there is some inhomogeneously distributed feature which triggers S-void formation, even in single-crystal interconnects. In summary, the authors feel that the strong crystallographic dependence of the S-voids, the possible effects of the enormous mechanical stresses (in excess of 1 GPa in some cases) which can exist in such interconnects, and the stochastic nature of the development of slit-like features, have not been adequately captured in the existing models. In what follows, the authors present a model for a role that dislocation pile-ups may play in reducing the energy of transition ofmore » E-voids to S-voids, and for controlling the location of this transition.« less

Stress Voiding in IC Interconnects: Rules of Evidence for Failure Analysts

Abstract Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.